LOW-POWER 9-BIT INVERTER FEATURES SY100S321 DESCRIPTION ■ Max. propagation delay of 700ps ■ IEE min. of –55mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ 70% faster than Fairchild 300K at lower power ■ Internal 75KΩ input pull-down resistors ■ Function and pinout compatible with Fairchild F100K ■ Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. O5 O6 O4 D4 VCCA VEES D5 PIN CONFIGURATIONS 11 10 9 8 7 6 5 D6 D7 VEE VEES VCCA 12 13 14 15 16 17 18 D8 D9 BLOCK DIAGRAM 4 3 2 1 28 27 26 Top View PLCC J28-1 O7 O8 VCCA VCC VCC O9 O1 D5 O5 D6 O6 D7 O7 D8 O8 D9 O9 VCCA O3 4 5 O2 6 D6 D7 D8 VCCA VEE D9 2 3 D5 17 16 D4 VCCA 15 14 Q4 Q5 13 7 8 9 10 11 12 Q6 Top View Flatpack F24-1 O8 O7 O4 D2 D3 24 23 22 21 20 19 18 VCCA D4 O3 1 O1 D3 D1 O9 VCC O2 VCCA O3 O2 D2 VEES O1 D2 D3 D1 D1 19 20 21 22 23 24 25 PIN NAMES Pin Function D1 – D9 Data Inputs Q1 – Q9 Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S321 Micrel DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter IIH Input HIGH Current IEE Power Supply Current Min. Typ. Max. Unit Condition — — 200 µA VIN = VIH (Max.) –55 –41 –25 mA Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter (1) tPLH tPHL Propagation Delay Data to Output tTLH tTHL Transition Time(1) 20% to 80%, 80% to 20% tS, G–G Skew, Gate-to-Gate TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit 300 800 300 800 300 800 ps 300 900 300 900 300 900 ps — 200 — 200 — 200 ps Condition NOTE: 1. Reference figures 1 and 2 PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter (1) tPLH tPHL Propagation Delay Data to Output tTLH tTHL Transition Time(1) 20% to 80%, 80% to 20% tS, G–G Skew, Gate-to-Gate TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit 300 700 300 700 300 700 ps 300 900 300 900 300 900 ps — 200 — 200 — 200 ps NOTE: 1. Reference figures 1 and 2 2 Condition SY100S321 Micrel TEST CIRCUITRY(1) L1 SCOPE CHAN A VCC RT 0.1µF L2 PULSE GENERATOR SCOPE CHAN B CIRCUIT UNDER TEST VEE RT 0.1µF Figure 1. AC Test Circuit NOTE: 1. VCC, VCCA = +2V, VEE = –2.5V. L1 and L2 = equal length 50Ω impedance lines. RT = 50Ω terminator internal to scope. Decoupling 0.1µF from GND to VCC and VEE. All unused outputs are loaded with 50Ω to GND. CL = Fixture and stray capacitance ≤ 3pF. SWITCHING WAVEFORMS 0.7 ± 0.1ns 0.7 ± 0.1ns –0.95V 80% 50% 20% INPUT –1.69V tPLH tPHL 80% 50% 20% OUTPUT tTLH tTHL Figure 2. Propagation Delay and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code 3 Package Type Operating Range SY100S321FC F24-1 Commercial SY100S321JC J28-1 Commercial SY100S321JCTR J28-1 Commercial SY100S321 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 4 SY100S321 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5