QUINT 2-INPUT OR/NOR GATE FEATURES The SY100S302 offers five 2-input OR/NOR gates designed for use in high-performance ECL systems. The five gates are controlled by a common Enable signal. All inputs have 75KΩ pull-down resistors and all outputs are buffered. Ob Ob Oa D1a Oa VEES PIN CONFIGURATIONS D2a 11 10 9 8 7 6 5 D1b D2b 12 13 14 15 16 17 18 VEE VEES E D1c D2c BLOCK DIAGRAM 4 3 2 1 28 27 26 Top View PLCC J28-1 Oc Oc VCCA VCC VCC Od Od D2a Oa D1b Ob D2b Ob Oc D2c Oc D1d Od D2d Od D1e Oe D2e Oe D1b D2c 1 24 23 22 21 20 19 18 D2a D2d D1e D2e 2 3 17 16 D1a Oa 15 14 Oa Ob 13 7 8 9 10 11 12 Ob Oe 4 5 Oe 6 Top View Flatpack F24-1 Od D1c D1d Oc Oc Oa Od VCC VCCA D1a D1c E VEE D2b 19 20 21 22 23 24 25 D2e Oe Oe ■ ■ ■ ■ Max. propagation delay of 700ps IEE min. of –45mA Industry standard 100K ECL levels Extended supply voltage option: VEE = –4.2V to –5.5V Voltage and temperature compensation for improved noise immunity Internal 75KΩ input pull-down resistors 50% faster than Fairchild 300K Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages D2d D1e VEES ■ DESCRIPTION D1d ■ ■ ■ ■ SY100S302 PIN NAMES Pin E Function Dna – Dne Data Inputs (n-1...5) E Enable Input Oa – Oe Data Outputs Oa – Oe Complementary Data Outputs VEES VEE Substrate VCCA VCCO for ECL Outputs Rev.: G 1 Amendment: /0 Issue Date: July, 1999 SY100S302 Micrel TRUTH TABLE(1) D1X D2X E OX OX L L L L H L L H H L L H L H L L H H H L H L L H L H L H H L H H L H L H H H H L NOTE: 1. H = High Voltage Level L = Low Voltage Level DC ELECTRICAL CHARACTERISTICS VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND Symbol Parameter Min. Typ. Max. Unit Condition IIH Input HIGH Current, All Inputs — — 200 µA VIN = VIH (Max.) IEE Power Supply Current –45 –28 –21 mA Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Data to Output 300 750 300 750 300 750 ps tPLH tPHL Propogation Delay Enable to Output 250 950 250 950 250 950 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps Condition PLCC VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit tPLH tPHL Propagation Delay Data to Output 250 700 250 700 250 700 ps tPLH tPHL Propogation Delay Enable to Output 250 900 250 900 250 900 ps tTLH tTHL Transition Time 20% to 80%, 80% to 20% 300 900 300 900 300 900 ps 2 Condition SY100S302 Micrel TIMING DIAGRAM 0.7 ± 0.1 ns 0.7 ± 0.1 ns INPUT –0.95V 80% 50% 20% –1.69V TRUE tPHL tPLH 50% OUTPUT tPLH tPHL 80% 50% 20% COMPLEMENT tTLH tTHL Propagation Delay and Transition Times NOTE: VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S302FC F24-1 Commercial SY100S302JC J28-1 Commercial SY100S302JCTR J28-1 Commercial 3 SY100S302 Micrel 24 LEAD CERPACK (F24-1) Rev. 03 4 SY100S302 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5