9-BIT HOLD REGISTER SY10E143 SY100E143 DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ The SY10/100E143 are high-speed 9-bit hold registers designed for use in new, high-performance ECL systems. The E143 can hold current data or load new data. The nine inputs, D0-D8, accept parallel input data. The SEL (Select) control pin serves to determine the mode of operation; either HOLD or LOAD. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR. The E143 is designed for applications requiring highspeed registers, pipeline registers, synchronous operation, and is also suitable for byte-wide parity. 700MHz min. operating frequency Extended 100E VEE range of –4.2V to –5.5V 9 bits wide for byte-parity applications Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75kΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E143 ■ Available in 28-pin PLCC package BLOCK DIAGRAM D Q1 D5 VCCO Q8 MUX SEL R D D1 PIN CONFIGURATION Q0 D8 D7 D6 D0 MUX R 25 24 23 22 21 20 19 D D Q3 17 28 16 15 Q6 VCC Q5 R D MUX PLCC TOP VIEW J28-1 1 14 VCCO D0 3 13 Q4 D1 4 12 Q3 2 Q4 5 6 D D5 MUX 8 9 10 11 Q5 R D D6 7 R D2 D3 D4 Q7 27 Q0 Q1 Q2 D3 18 CLK1 CLK2 VEE NC Q2 R MUX 26 D4 VCCO D2 MUX MR MUX PIN NAMES Q6 R Pin D Q7 Function D0-D8 Parallel Data Inputs SEL Mode Select Input CLK1, CLK2 Clock Inputs MR Master Reset SEL Q0-Q8 Data Outputs CLK1 NC No Connection CLK2 VCCO VCC to Output D7 D8 MUX MUX R D Q8 R MR Rev.: D 1 Amendment: /0 Issue Date: August, 1998 SY10E143 SY100E143 Micrel TRUTH TABLE SEL MODE L LOAD H HOLD DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter IIH Input HIGH Current IEE Power Supply Current TA = +25°C Min. Typ. Max. 10E 100E Min. Typ. TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — — — 150 — — 150 — — 150 — — 120 120 145 145 — — 120 120 145 145 — — 120 138 145 165 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Min. Typ. Max. Min. Typ. TA = +85°C Max. Unit Condition fMAX Max. Toggle Frequency 700 900 — 700 900 — 700 900 — MHz — tPLH tPHL Propagation Delay to Output CLK MR ps — 600 600 800 800 1000 1000 600 600 800 800 1000 1000 600 600 800 800 1000 1000 tS Set-up Time D SEL ps — 50 300 –100 150 — — 50 300 –100 150 — — 50 300 –100 150 — — Hold Time D SEL ps — 300 75 100 –150 — — 300 75 100 –150 — — 300 75 100 –150 — — tRR Reset Recovery Time 900 700 — 900 700 — 900 700 — ps — tPW Minimum Pulse Width CLK, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 75 — — 75 — — 75 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 525 800 300 525 800 300 525 800 ps — tH Parameter TA = +25°C Max. NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E143JC J28-1 Commercial SY10E143JCTR J28-1 Commercial SY100E143JC J28-1 Commercial SY100E143JCTR J28-1 Commercial 2 Min. Typ. SY10E143 SY100E143 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E143 SY100E143 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4