5V/3.3V ÷2, ÷4, ÷8 CLOCK GENERATION CHIP FEATURES ■ ■ ■ ■ ■ DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The V BB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system. 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors ■ Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM Q0 1 Q Q0 2 16 VCC 15 EN 14 NC 13 CLK 12 CLK 11 VBB 10 MR 9 VEE ÷2 R Q D VCC 3 R Q1 4 Q Q1 5 ÷4 R VCC 6 Q2 7 Q Q2 8 ClockWorks™ SY10EL34/L SY100EL34/L ÷8 R SOIC TOP VIEW PIN NAMES Pin Function CLK Differential Clock Inputs EN Synchronous Enable MR Master Reset VBB Reference Output Q0 Differential ÷2 Outputs Q1 Differential ÷4 Outputs Q2 Differential ÷8 Outputs Rev.: F 1 Amendment: /0 Issue Date: August, 1998 ClockWorks™ SY10EL34/L SY100EL34/L Micrel TRUTH TABLE CLK EN MR Z L L Divide Function ZZ H L Hold Q0–2 X X H Reset Q0–2 NOTE: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition DC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter 10EL 100EL TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — — — — 49 49 — — — — 49 49 — — — — 49 49 — — — — 49 54 mA — — –1.19 –1.26 V — 150 µA IEE Power Supply Current VBB Output Reference 10EL –1.43 Voltage 100EL –1.38 — — IIH Input High Current — NOTE: 1. Parametric values specified at: TA = 0°C — –1.30 –1.38 –1.26 –1.38 150 5 volt Power Supply Range 3 volt Power Supply Range — — — –1.27 –1.35 –1.26 –1.38 — 150 100EL34 Series: 10EL34 Series 10/100EL34L Series: — — — — –1.25 –1.31 –1.26 –1.38 150 — -4.2V to -5.5V. -4.75V to -5.5V. -3.0V to -3.8V. AC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol TA = 0°C TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit tPLH tPHL Propagation Delay to Output CLK MR 960 650 1100 800 1200 1010 960 650 1100 800 1200 1010 960 650 1100 800 1200 1010 960 650 1100 1200 800 1010 tskew Within-Device Skew(2) — — 50 — — 50 — — 50 — — 50 ps tS Set-up Time EN 400 — — 400 — — 400 — — 400 — — ps tH Hold Time EN ps 200 — — 200 — — 200 — — 200 — — ps Minimum Input Swing(3) 250 — — 250 — — 250 — — 250 — — mV VCMR Common Mode Range(4) –1.3 — –0.4 –1.4 — –0.4 –1.4 — –0.4 –1.4 — –0.4 V tr tf Output Rise/Fall Times Q (20% – 80%) 275 400 525 275 400 525 275 400 525 275 400 525 ps VPP NOTES: 1. Parametric values specified at: 5 volt Power Supply Range 100EL34 Series: 10EL34 Series 10/100EL34L Series: -4.2V to -5.5V. -4.75V to -5.5V. -3.0V to -3.8V. 3 volt Power Supply Range 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I. 2 ClockWorks™ SY10EL34/L SY100EL34/L Micrel TIMING DIAGRAM Internal Clock Disabled Internal Clock Enabled CLK Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. PRODUCT ORDERING CODE 5V 3.3V Ordering Code Package Type Operating Range VEE Range (V) Ordering Code SY10EL34LZC Z16-2 Commercial -3.0 to -3.8 SY10EL34LZCTR Z16-2 Commercial SY100EL34LZC Z16-2 SY100EL34LZCTR Z16-2 Package Type Operating Range VEE Range (V) SY10EL34ZC Z16-2 Commercial -4.75 to -5.5 -3.0 to -3.8 SY10EL34ZCTR Z16-2 Commercial -4.75 to -5.5 Commercial -3.0 to -3.8 SY100EL34ZC Z16-2 Commercial -4.2 to -5.5 Commercial -3.0 to -3.8 SY100EL34ZCTR Z16-2 Commercial -4.2 to -5.5 3 ClockWorks™ SY10EL34/L SY100EL34/L Micrel 16 LEAD SOIC .150" WIDE (Z16-2) Rev. 02 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4