ONSEMI MC100EL34

SEMICONDUCTOR TECHNICAL DATA
÷ ÷ ÷
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the VBB output, a sinusoidal
source can be AC coupled into the device (see Interfacing section of the
ECLinPS Data Book DL140/D). If a single-ended input is to be used, the
VBB output should be connected to the CLK input and bypassed to ground
via a 0.01µF capacitor. The VBB output is designed to act as the switching
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
•
•
•
•
•
50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
75kΩ Internal Input Pulldown Resistors
>1000V ESD Protection
PIN DESCRIPTION
PIN
FUNCTION
CLK
EN
MR
VBB
Q0
Q1
Q2
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff ÷2 Outputs
Diff ÷4 Outputs
Diff ÷8 Outputs
FUNCTION TABLE
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC
EN
NC
CLK
CLK
VBB
MR
VEE
16
15
14
13
12
11
10
9
D
Q
EN
MR
Z
L
L
Divide
ZZ
H
L
Hold Q0–3
X
X
H
Reset Q0–3
R
÷2
Q
R
÷4
Q
R
÷8
Q
R
1
2
3
4
5
6
7
8
Q0
Q0
VCC
Q1
Q1
VCC
Q2
Q2
Z = Low-to-High Transition
ZZ = High-to-Low Transition
12/93
 Motorola, Inc. 1996
3–1
FUNCTION
CLK
REV 2
MC10EL34 MC100EL34
AC/DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND)
–40°C
Symbol
Characteristic
Min
Typ
0°C
Max
Min
Typ
Max
Min
Typ
Max
Typ
Max
Power Supply
Current
VBB
Output Reference 10EL
Voltage
100EL
IIH
Input High Current
150
tPLH
tPHL
Propagation CLK→Q0
Delay to
CLK→Q1,2
Output
MR→Q
960
900
750
tSKEW
Within-Device Skew
tS
Setup Time EN
400
400
400
400
ps
tH
Hold Time EN
250
250
250
250
ps
VPP
Minimum Input Swing
CLK
250
250
250
250
Common Mode Range
CLK
–2.0
–0.4
–2.0
–0.4
–2.0
–0.4
–2.0
–0.4
275
525
275
525
275
525
275
525
Output Rise/Fall Times Q
(20% – 80%)
39
39
–1.43
–1.38
–1.30
–1.26
1100
Unit
IEE
10EL
100EL
1100
Min
Max Toggle Frequency
tr
tf
1100
85°C
fMAX
VCMR
1100
25°C
39
39
–1.38
–1.38
–1.27
–1.26
39
39
–1.35
–1.38
–1.25 –1.31
–1.26 –1.38
150
1200
1140
1060
960
900
750
100
1200
1140
1060
MHz
150
960
900
750
100
1200
1140
1060
970
910
790
100
39
42
mA
–1.19
–1.26
V
150
µΑ
1210
1150
1090
ps
100
ps
mV
V
Internal Clock
Disabled
ps
Internal Clock
Enabled
CLK
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state
during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner, time and relationship as they would have had the EN signal not been asserted.
Figure 1. Timing Diagram
MOTOROLA
3–2
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC10EL34 MC100EL34
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
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◊
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3–3
*MC10EL34/D*
MC10EL34/D
MOTOROLA