MICREL SY100S834LZC

(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)
CLOCK GENERATION CHIP
Micrel, Inc.
Precision Edge®
SY100S834
PrecisionSY100S834L
Edge®
SY100S834
SY100S834L
FEATURES
■
■
■
■
■
■
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master Reset for synchronization
Internal 75KΩ input pull-down resistors
Available in 16-pin SOIC package
Precision Edge®
DESCRIPTION
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,
÷4, ÷8) clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the VBB output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FSEL input
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
TRUTH TABLE
CLK
EN
MR
Function
Z
L
L
Divide
ZZ
H
L
Hold Q0–2
X
X
H
Reset Q0–2
Notes:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
FSEL
Q0 Outputs
Q1 Outputs
Q2 Outputs
L
Divide by 2
Divide by 4
Divide by 8
H
Divide by 1
Divide by 2
Divide by 4
PIN NAMES
Pin
Function
CLK
Differential Clock Inputs
FSEL
Function Select
EN
Synchronous Enable
MR
Master Reset
VBB
Reference Output
Q0
Differential ÷1 or ÷2 Outputs
Q1
Differential ÷2 or ÷4 Outputs
Q2
Differential ÷4 or ÷8 Outputs
Precision Edge is a registered trademark of Micrel, Inc.
M9999-032206
[email protected] or (408) 955-1690
Rev.: G
1
Amendment: /0
Issue Date: March 2006
Precision Edge®
SY100S834
SY100S834L
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information
Q0 1
16 VCC
Q
÷1 or ÷2
Q0
2
R
VCC 3
15
Q
D
R
Q1 4
14
EN
F SEL
13 CLK
Q
Q1 5
÷2 or ÷4
R
VCC 6
Q2
7
Q2
8
R
Operating
Range
Package
Marking
Lead
Finish
SY100S834ZC
Z16-2
Commercial
SY100S834ZC
Sn-Pb
SY100S834ZCTR(1)
Z16-2
Commercial
SY100S834ZC
Sn-Pb
SY100S834LZC
Z16-2
Commercial
SY100S834LZC
Sn-Pb
SY100S834LZCTR(1)
Z16-2
Commercial
SY100S834LZC
Sn-Pb
SY100S834ZI
Z16-2
Industrial
SY100S834ZI
Sn-Pb
12 CLK
SY100S834ZITR(1)
Z16-2
Industrial
SY100S834ZI
Sn-Pb
11 VBB
SY100S834LZI
Z16-2
Industrial
SY100S834LZI
Sn-Pb
SY100S834LZITR(1)
Z16-2
Industrial
SY100S834LZI
Sn-Pb
SY100S834ZG(2)
Z16-2
Industrial
SY100S834ZG with
NiPdAu
Pb-Free bar-line indicator Pb-Free
SY100S834ZGTR(1, 2)
Z16-2
Industrial
SY100S834ZG with
NiPdAu
Pb-Free bar-line indicator Pb-Free
SY100S834LZG(2)
Z16-2
Industrial
SY100S834LZG with
NiPdAu
Pb-Free bar-line indicator Pb-Free
SY100S834LZGTR(1, 2)
Z16-2
Industrial
SY100S834LZG with
NiPdAu
Pb-Free bar-line indicator Pb-Free
10
MR
9
VEE
Q
÷4 or ÷8
Package
Type
Part Number
16-Pin SOIC (Z16-2)
Notes:
1. Tape and Reel.
2. Pb-Free package is recommended for new designs.
M9999-032206
[email protected] or (408) 955-1690
2
Precision Edge®
SY100S834
SY100S834L
Micrel, Inc.
DC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
Symbol
Parameter
TA = 0°C
TA = +25°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
—
—
49
—
—
49
—
—
49
—
—
54
mA
—
-1.26
V
—
150
µA
IEE
Power Supply Current
VBB
Output Reference Voltage -1.38
—
-1.26
-1.38
—
-1.26
-1.38
—
IIH
Input HIGH Current
—
150
—
—
150
—
—
—
Note:
1. Parametric values specified at:
TA = +85°C
5 volt Power Supply Range
3 volt Power Supply Range
100S834 Series:
100S834L Series
-1.26 -1.38
150
—
-4.2V to -5.5V.
-3.0V to -3.8V.
AC ELECTRICAL CHARACTERISTICS(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
Symbol
Parameter
TA = +25°C
TA = +85°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
960
650
1100
800
1200
1010
960
650
1100
800
1200
1010
960
650
1100
800
1200
1010
960
650
1100 1200
800 1010
ps
—
—
50
—
—
50
—
—
50
—
—
50
ps
ps
tPLH
tPHL
Propagation Delay
to Output
tskew
Within-Device Skew(2)
tS
Set-up Time EN
400
—
—
400
—
—
400
—
—
400
—
—
tH
Hold Time EN
200
—
—
200
—
—
200
—
—
200
—
—
ps
VPP
Minimum Input Swing
250
—
—
250
—
—
250
—
—
250
—
—
mV
VCMR
Common Mode Range(3)
CLK
–1.3
—
–0.4
–1.4
—
–0.4
–1.4
—
–0.4
–1.4
—
–0.4
V
275
400
525
275
400
525
275
400
525
275
400
525
ps
tr
tf
CLK
MR
TA = 0°C
Output Rise/Fall Times
Q (20% – 80%)
Notes:
1. Parametric values specified at:
5 volt Power Supply Range 100S834 Series:
-4.2V to -5.5V.
3 volt Power Supply Range 100S834L Series -3.0V to -3.8V.
2. Within-Device Skew is specified for identical transition.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I.
M9999-032206
[email protected] or (408) 955-1690
3
Precision Edge®
SY100S834
SY100S834L
Micrel, Inc.
TIMING DIAGRAM
Internal Clock
Disabled
CLK
FSEL = 0
Q0
Q1
Q2
FSEL = 1
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain
their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their
next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
M9999-032206
[email protected] or (408) 955-1690
4
Precision Edge®
SY100S834
SY100S834L
Micrel, Inc.
16-PIN SOIC .150" WIDE (Z16-2)
Rev. 02
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
USA
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-032206
[email protected] or (408) 955-1690
5