125MHz TRIGGER PROGRAMMABLE TIMING EDGE VERNIER DESCRIPTION FEATURES ■ True 125MHz retrigger rate Micrel-Synergy's SY604 is an ECL-compatible timing vernier (delay generator) whose time delay is programmed via an 8bit code which is loaded concurrently with the circuit trigger. The SY604 is fabricated in Micrel-Synergy's proprietary ASSET™ bipolar process. This device can be retriggered at speeds up to 125MHz, with a delay span as short as 4ns. At minimum span, the resolution is 4ns/255 = 15.7ps per step. The delay span is externally adjustable up to 40ns. The SY604 employs differential TRIGGER inputs, and produces a differential OUTPUT pulse; all other control signals are single-ended ECL. Edge delay is specified by an 8-bit input which is loaded into the device with the TRIGGER. The output pulse width will typically be 3.5ns. The SY604 is commonly used in Automatic Test Equipment to provide precise timing edge placement; it is also found in many instrumentation and communications applications. Micrel-Synergy's circuit design techniques coupled with ASSET™ technology result in not only ultra-fast performance, but allow device operation at lower power dissipation than competing technologies. Outstanding reliability is achieved in volume production. ■ Pin-compatible with Bt604 ■ 15ps delay resolution ■ Less than ± 1 LSB timing accuracy ■ Differential TRIGGER inputs ■ Delay spans from 4 to 40ns ■ Compatible with 10KH ECL logic ■ Lower power dissipation 350mW typical ■ Available in 28-pin plastic (PLCC) or metal (MLCC) J-lead package BLOCK DIAGRAM D0 - D7 SY604 8 8 I/V DAC LATCH PIN CONFIGURATION 0 = STOP 25 24 23 22 21 20 19 R IEXT 26 18 NC D1 D2 D3 27 17 COMP2 CE COMP1 D4 D5 2 D6 4 28 TOP VIEW PLCC J28-1 1 3 5 6 7 8 9 TRIG VEE0 VEE0 TRIG D0 VEE1 1 = RUN TRIG FF VCC VCC NC LINEAR RAMP GENERATOR D VCC OUT OUT VCC CE OUT D7 V BB PULSE GEN VEE1 + – 16 15 14 13 NC VBB 12 IEXT 10 11 Rev.: E 1 Amendment: /0 Issue Date: May, 1998 SY604 Micrel PIN DESCRIPTION OUT, OUT Differential outputs (ECL compatible). D0 – D7 Data input pins (ECL compatible). On the rising edge of TRIG, a ramp is initiated whereupon D0-D7 are latched into the device. D0 is the LSB. These inputs specify the amount of delay from the rising edge of TRIG to the output pulse. IEXT Current reference pin. The amount of current sourced into this pin determines the span of output delay. The voltage at IEXT is typically –1.25V. CE Chip enable input (ECL compatible). CE must be a logical zero on the rising edge of TRIG to enable the device to respond to the trigger. If CE is floating, the trigger will always be enabled. COMP1, COMP2 Compensation pins. A 0.1µF ceramic capacitor must be connected between COMP1 and VEE0, and COMP2 and VEE0 (see Figure 3). TRIG, TRIG Differential trigger inputs (ECL compatible). The rising edge of TRIG is used to trigger the delay cycle if CE is a logical zero. If CE is a logical one, no operation occurs. It is recommended that triggering be performed with differential inputs. VEE Device power. All VEE pins must be connected. VCC Device ground. All VCC pins must be connected together. VBB A –1.36V (typical) output. FUNCTIONAL DESCRIPTION The output pulse generation cycle begins with the arrival of TRIG shown in Figure 1. When TRIG transitions to a high and CE is low, the values on D0 - D7 are latched, thereby setting the DAC values. Simultaneously with the latching of D0 - D7, the linear ramp generator is enabled. When the ramp level reaches that of the DAC, the comparator initiates the pulse generator to produce an output pulse of fixed width. The generation of an output pulse resets the ramp and the cycle is ready to begin again. DATA D0 - D7 CE TRIG OUT Figure 1. 2 SY604 Micrel ABSOLUTE MAXIMUM RATING(1) Symbol Parameter VEE Power Supply (VCC = 0V) VI Input Voltage (VCC = 0V) IOUT Output Current — Continuous — Surge Value Unit -8 to 0 V 0 to VEE V mA 50 100 TA Operating Temperature Range VEE Operating Range(2) 0 to +85 ˚C -5.7 to -4.2 V NOTES: 1. Beyond which device life may be impaired. 2. Parametric values specified at 10E Series: - 4.75V to - 5.5V. DC CHARACTERISTICS(1) TA = +0˚C Symbol Parameter TA = +25˚C TA = +70˚C Min. Typ. Max. MIn. Typ. Max. Min. Typ. Max. Unit -1170 — -840 -1130 — -810 -1070 — -735 mV VIH Input HIGH Voltage (10K) VIL Input LOW Voltage (10K) -1950 — -1480 -1950 — -1480 -1950 — -1450 mV VOH Output HIGH Voltage (10K) -1020 -975 -840 -980 -920 -810 -920 -850 -735 mV VOL Output LOW Voltage (10K) -1950 -1755 -1630 -1950 -1750 -1630 -1950 -1720 -1600 mV IIH IIH Input High Current (Vin = VIH max) TRIG, TRIG — — 100 100 150 150 — — 100 100 150 150 — — 100 100 150 150 µA µA IIL IIL Input Low Current (Vin = VIL min) TRIG, TRIG — — 100 100 150 150 — — 100 100 150 150 — — 100 100 150 150 µA µA DL IL Output Delay Spans Differential Linearity Error** Integral Linearity Error** — — ±0.84 ±1.16 ±0.9 ±1.25 — — ±0.84 ±0.89 ±0.9 ±1.0 — — ±0.84 ±0.89 ±0.9 ±1.0 LSB VBB VBB Output Voltage -1.44 — -1.25 -1.44 -1.35 -1.25 -1.44 — -1.25 V IEXT IEXT for Tspans Tspan = 4ns Tspan = 5ns Tspan = 10ns Tspan = 15ns Tspan = 20ns Tspan = 30ns 1.80 1.45 0.70 0.45 0.34 0.20 2.38 1.85 0.93 0.62 0.46 0.30 2.80 2.40 1.20 0.80 0.60 0.40 1.80 1.45 0.70 0.45 0.34 0.20 2.38 1.85 0.93 0.62 0.46 0.30 2.80 2.40 1.20 0.80 0.60 0.40 1.80 1.45 0.70 0.45 0.34 0.20 2.38 1.85 0.93 0.62 0.46 0.30 2.80 2.40 1.20 0.80 0.60 0.40 mA mA mA mA mA mA Tspan with IEXT = 1.8 mA (Tspan = Tmax - Tmin) 4.1 — 6.5 4.1 — 6.5 4.1 — 6.5 ns Minimum Delay Time* Data = 00, Tspan = 5ns Tspan = 10ns Tspan = 15ns Tspan = 20ns Tspan = 25ns Tspan = 30ns — — — — — — 2.8 3.4 4.0 4.6 5.2 5.8 3.8 4.9 6.0 7.1 8.2 9.3 — — — — — — 2.8 3.4 4.0 4.6 5.2 5.8 3.8 4.9 6.0 7.1 8.2 9.3 — — — — — — 2.8 3.4 4.0 4.6 5.2 5.8 3.8 4.9 6.0 7.1 8.2 9.3 ns ns ns ns ns ns VEE Supply Current — — 100 — 70 100 — — 100 mA Tmin IEE NOTE: 1. 10K series circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor to -2.0 volts. 3 SY604 Micrel AC CHARACTERISTICS ECL input values are -0.9 to -1.7V, with input rise/fall times ≤ 2ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. OUT and OUT loading with 50Ω to -2.0V. Typical values are based on nominal temperature, i.e., and nominal voltage, i.e., -5.2V. TA = +0˚C Symbol Parameter (1) TA = +25˚C TA = +70˚C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — — 125 — — 125 — — 125 MHz fMAX Trigger Rate tWI Trigger Width High 2.0 1.0 — 2.0 1.0 — 2.0 1.0 — ns tWO Output Pulse Width High Time Output Pulse Rise/Fall Time (20/80%) Output Pulse Spacing Span = 4ns @ 1 LSB 2.5 — 3.5 550 4.5 750 2.5 — 3.5 550 4.5 750 2.5 — 3.5 550 4.5 750 ns ps 8.0 — — 8.0 — — 8.0 — — ns — 125 220 — 125 220 — 125 220 ps/ns 4.0 15.7 — — 40 157 4.0 15.7 — — 40 157 4.0 15.7 — — ns 40 157 ns ps — — — 2 2 60 — — — — — — 2 2 60 — — — — — — 2 2 60 — — — ps/˚C ps/˚C ps/V tS Minimum Delay Time vs. Tspan ∆ T00 / ns (Tspan = 5 to 10ns) 1 LSB 1 LSB Output Delay Tspan (Tspan = Tmax - Tmin) Resolution (Tspan / 225) Tempo (5ns Span) ∆ Tspan / ˚C ∆ Tmin / ˚C Power Supply Rejection (Data = 0-FF HEX, Tspan = 5ns) tS tH CE Setup Time CE Hold Time 2.0 1.5 — — — — 2.0 1.5 — — — — 2.0 1.5 — — — — ns ns tWH tDS tDH WRITE Pulse Width High Time D0 - D7 Setup Time D0 - D7 Hold Time 2.0 1.0 1.5 — — — — — — 2.0 1.0 1.5 — — — — — — 2.0 1.0 1.5 — — — — — — ns ns ns NOTE: 1. See chart below: Maximum Tspan and Trigger Rates Maximum Tspan (ns) Maintaining Linearity Minimum Trigger Periods (ns) of ± 1 LSB 4.0 8.0 5.1 10.0 5.8 11.1 6.75 12.5 8.1 14.3 9.9 16.6 12.0 20.0 15.5 25.0 22.0 33.3 The information in this table is guaranteed but not 100% production tested. See Figure 2 for a graphical representation. 4 SY604 Micrel TIMING DIAGRAMS tWI TRIG tSU tH CE DATA D0 - D7 tWO DELAY OUT tS ± 1 LSB Span vs. Trigger Rates 9 INL - 0.92LSB 8 Span (ns) 7 INL - 0.86LSB 6 INL - 0.9LSB 5 INL - 1.14LSB 4 3 2 60 70 80 90 100 110 120 130 Frequency (MHz) Figure 2. 5 SY604 Micrel APPLICATION DIAGRAM VEE1 VEE0 –5.2V SY604 C3 C2 C4 C1 COMP1 COMP2 VCC GROUND REXT I IEXT ZO = 50Ω VEXT ZO = 50Ω TRIG OUT –2.0V –2.0V 50Ω 50Ω ZO = 50Ω ZO = 50Ω TRIG OUT* –2.0V –2.0V 50Ω 50Ω REXT Calculation: REXT = (VEXT + 1.25V)/IEXT For Example: If Tspan is around 15ns, then IEXT is around 0.6mA, (see DC Characteristic Table) and assume IEXT pin is tied to VCC with the resistor. REXT = 0 + 1.25V/0.6mA = 2.08K ohm Location Description Vendor Part Number C1–C4 0.1µF ceramic capacitor Erie RPE112Z5U104M50V REXT 1% metal film resistor (selected for proper Tspan) CB301210 Dale CMF-55C NOTE: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the SY604. All devices should be as close as possible to the SY604. Figure 3. Typical Connection Diagram and Parts List. PRODUCT ORDERING CODE Ordering Code 6 Package Type Operating Range SY604JC J28-1 Commercial SY604JCTR J28-1 Commercial SY604 Micrel 7 SY604 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 8