DESIGN FEATURES 16-Bit Parallel DAC Has 1LSB Linearity, Ultralow Glitch and Accurate by Patrick Copley 4-Quadrant Resistors Today’s fast paced marketplace has developed a major appetite for high resolution, high accuracy, fast digital-to-analog converters. System requirements in instrumentation, automatic test equipment, communications, waveform generation, data acquisition and feedback control systems, among many other applications, have fueled the need for 16-bit digitalto-analog converters. Not only does the converter need to meet the stringent speed and accuracy requirements of the system, it needs to do so in both unipolar (0V to 10V) and bipolar (±10V) modes of operation without degradation. To meet and exceed these requirements, Linear Technology introduces its LTC1597 16-bit parallel, current output, low glitch, multiplying DAC with 4-quadrant resistors. Key features of the new DAC include: ❏ ±1LSB maximum INL and DNL over the industrial temperature range ❏ On-chip 4-quadrant resistors allow precise 0V to 10V, 0V to –10V or ±10V outputs ❏ Ultralow, < 1nV-s midscale glitch impulse ❏ Small 28-pin SSOP package ❏ Low supply power consumption: 10µW typical ❏ Pin-compatible with the LTC1591 14-bit parallel, current output, low glitch, multiplying DAC with 4-quadrant resistors. Unique Features of the LTC1597 The LTC1597 operates from a single 5V supply and provides both unipolar 48k REF 0V to –10V or 0V to 10V and bipolar ±10V output ranges from a 10V or –10V reference input using a single or dual external op amp. The device achieves bipolar operation using three additional on-chip precision resistors. The DAC consists of a precision thinfilm R/2R ladder for the thirteen LSBs. The three MSBs are decoded into seven segments of resistor value R, as shown in Figure 1. R is nominally 48k. Each of these segments and the R/2R ladder carry an equally weighted current of one-eight of full-scale. The feedback resistor, RFB, and 4-quadrant resistor, ROFS, have a value of R/ 4. 4-quadrant resistors R1 and R2 have a magnitude of R/4. The reference pin presents a constant input impedance of R/8 in unipolar mode and R/12 in bipolar mode. The output impedance of the current output pin, IOUT1, varies with DAC code. 48k 1 R2 12k RCOM 2 48k 48k 48k 48k 48k 48k 48k 96k 96k 96k 96k ROFS 12k RFB 12k 4 ROFS 5 RFB R1 12k R1 3 6 IOUT1 VCC 23 7 AGND DECODER LD 8 WR 9 LOAD 22 DGND D15 (MSB) D14 D12 D13 D11 ••• DAC REGISTER D0 (LSB) RST INPUT REGISTER WR 28 CLR RST 1597 BD 10 11 D15 D14 •••• 21 24 25 26 27 D4 D3 D2 D1 D0 Figure 1. The LTC1597 16-bit CMOS DAC uses a precision thin-film modified R/2R architecture to provide unsurpassed accuracy and stability. Accurate 4-quadrant multiplication applications are now possible with on-chip resistors R1, R2 and ROFS. A built-in deglitcher reduces glitch impulse to 1nV-s. 18 Linear Technology Magazine • February 1999 DESIGN FEATURES 1.0 16-Bit Accuracy Over Temperature INTEGRAL NONLINEARITY (LSB) 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 0 49152 32768 16384 DIGITAL INPUT CODE 2a. 65535 1597 G01 DIFFERENTIAL NONLINEARITY (LSB) 1.0 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535 1597 G02 2b. Figure 2. The outstanding INL and DNL (typically less than 0.25LSB) and very low linearity drift allow a maximum 1LSB spec to be guaranteed over the industrial temperature range. An added feature of the LTC1597 is a proprietary deglitcher that reduces the glitch energy to below 1nV-s over the DAC’s output voltage range. The LTC1597 has a 16-bit parallel input data bus and is double buffered with two 16-bit registers. The double buffered feature permits the updating of several DACs simultaneously. The WR signal updates the input register and the LD signal loads the DAC register. The deglitcher is activated on the rising edge of the LD signal. The versatility of the interface also allows the use of the input and DAC registers in a master/slave or edgetriggered configuration. This mode of operation occurs when WR and LD are tied together to act as a clock signal. The asynchronous clear pin (CLR) resets the LTC1597 to zero scale and the LTC1597-1 to midscale. CLR resets both the input and DAC registers. The LTC1597 also features a poweron reset. Linear Technology Magazine • February 1999 The LTC1597 has ultralow linearity drift of well below ±0.2LSB from –45°C to 85°C. This allows the LTC1597 to hold its accuracy of 1LSB integral nonlinearity (INL) and differential nonlinearity (DNL) over time and temperature. In the past, the only DACs that approached this accuracy over temperature were of the autocalibrated type. These DACs were very large, very expensive and therefore not very practical for most applications. Figures 2a and 2b show the typical INL and DNL curves of the LTC1597. The outstanding 0.25LSB INL, 0.15 LSB DNL (typical) and very low drift allow a maximum 1LSB specification over the extended industrial temperature range. For optimum performance, the REF pin of the LTC1597 should be driven by a source impedance of less than 1kΩ. However, the DAC has been designed to minimize source impedance effects. An 8kΩ source impedance degrades both INL and DNL by a mere 0.2LSB. 5V LD PULSE 5V/DIV GATED SETTLING WAVEFORM 500µV/DIV 500ns/DIV Figure 4. When used with the LT1468 and a 20pF feedback capacitor (see Figure 3), the LTC1597 can settle in an amazing 1.7µs to within 0.0015%. The top trace shows the LD pulse; the bottom trace shows the gated settling waveform settling to 1LSB in 1.7µs. Fast Settling: Less than 2µs to within 0.0015% of Full-Scale Now system designers no longer have to make tough decisions in the tradeoff between accuracy and speed. The solution is here. The combination of the LTC1597 DAC and the LT1468 op amp provides an industry first: superb 16-bit settling of less than 2µs for a 10V step while maintaining 1LSB DC accuracy. Figure 3 shows the application circuit for unipolar mode. Figure 4 shows the resulting full-scale 10V step settling time of the LTC1597/LT1468 combination. With a 20pF feedback capacitor, the optimized settling time to 0.0015% is an amazing ≈1.7µs. A 0.1µF VREF 2 3 R1 1 REF RCOM R1 23 VCC 4 5 ROFS RFB ROFS R2 20pF RFB IOUT1 16 DATA INPUTS LTC1597 – 6 16-BIT DAC AGND 10 TO 21, 24 TO 27 DGND 7 + LT1468 VOUT = 0V TO –VREF 22 WR LD CLR WR LD CLR 9 8 28 Unipolar Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1000 0000 0000 ANALOG OUTPUT VOUT 1111 0000 0000 0000 1111 0000 0000 0000 1111 0000 0001 0000 –VREF (65,535/65,536) –VREF (32,768/65,536) = –VREF/2 –VREF (1/65,536) 0V 1591/97 F01b Figure 3. With a single external op amp, the LTC1597 performs 2-quadrant multiplication with ±10V input and 0V to –VREF output. With a fixed –10V reference, it provides a precision 0V to 10V unipolar output. 19 DESIGN FEATURES – 50 – 60 – 70 – 80 500kHz FILTER – 90 80kHz FILTER –100 30kHz FILTER –110 10 100 1k 10k FREQUENCY (Hz) – 50 – 40 VCC = 5V USING TWO LT1468s CFEEDBACK = 15pF REFERENCE = 6VRMS – 60 – 70 – 80 500kHz FILTER – 90 –100 80kHz FILTER 10 100 – 60 – 70 – 80 500kHz FILTER – 90 80kHz FILTER –100 –110 1k 10k FREQUENCY (Hz) 1591/97 G03 VCC = 5V USING TWO LT1468s CFEEDBACK = 15pF REFERENCE = 6VRMS – 50 30kHz FILTER 30kHz FILTER –110 100k 6a. Unipolar-mode full-scale: the noise and distortion (N + D) is less than –96dB for signal frequencies up to 30kHz. Out to 100kHz, the N + D is less than –78dB. SIGNAL/(NOISE + DISTORTION) (dB) – 40 VCC = 5V USING AN LT1468 CFEEDBACK = 30pF REFERENCE = 6VRMS SIGNAL/(NOISE + DISTORTION) (dB) SIGNAL/(NOISE + DISTORTION) (dB) – 40 10 100k 100 1k 10k FREQUENCY (Hz) 100k 1591/97 G05 1591/97 G04 6b. Bipolar-mode zero-scale: the N + D is less than –96dB for signal frequencies up to 30kHz. Out to 100kHz, the N + D is less than –82dB. 6c. Bipolar-mode full-scale: the (N + D) is less than –96dB for signal frequencies up to 30kHz. Out to 100kHz, the N + D is less than –79dB. Figure 6. LTC1597 multiplying-mode signal-to-noise vs frequency detailed discussion of 16-bit settling time can be found in Linear Technology Application Note 74, “Component and Measurement Advances Ensure 16-Bit DAC Settling Time.” The ability to minimize settling time is limited by the need to null the DAC output capacitance, which varies from 70pF to 115pF, depending on code. This capacitance at the amplifier input combines with the feedback resistor to form a zero in the closed-loop frequency response in the vicinity of 200kHz–400kHz. Without a feedback capacitor, the circuit will oscillate. The choice of 20pF stabilizes the circuit by adding a pole at 1.3MHz to limit the frequency peaking and also optimizes settling time. The settling time to 16-bit accuracy is theoretically bounded by 11.1 time constants set by the feedback resistance and capacitance. OUTPUT VOLTAGE (mV) +10 Glitches in a DAC’s output when it updates can be a big problem in precision applications. Usually, the worst-case glitch occurs when the DAC output crosses midscale. The LTC1597’s new proprietary deglitcher reduces the output glitch impulse to 1nV-s, which is at least ten times lower than any of the competition’s 16-bit voltage output DACs. In addition, the deglitcher makes the glitch impulse uniform for any code. Figure 5 shows the output glitch for a midscale transition with a 0V to 10V output range. Unipolar 0V to 10V Outputs with a Single Op Amp Figure 3 shows the circuit for a 0V to 10V output range. The DAC uses an external reference and a single op amp in this configuration. This circuit can also perform 2-quadrant multiplication where the REF pin is driven by a ±10V AC input signal and VOUT swings from 0V to –VREF. VREF + 5V 0.1µF 1/2 LT1112 – 2 3 R1 1 REF RCOM R1 5 23 4 VCC ROFS ROFS R2 RFB 33pF RFB IOUT1 16 DATA INPUTS LTC1597-1 – 6 1/2 LT1112 16-BIT DAC AGND 10 TO 21, 24 TO 27 COMPETITOR’S DAC DGND 7 + VOUT = –VREF TO VREF 22 WR LD CLR WR LD CLR 0 1nV-s TYP LTC1597 –10 9 8 28 Bipolar Offset Binary Code Table DIGITAL INPUT BINARY NUMBER IN DAC REGISTER 1 2 TIME (µs) 3 4 03 .eps Figure 5. The proprietary deglitcher 1595 reduces the output glitch to less than 1nV-s, which is ten times less than any other 16-bit, voltageoutput DAC. Further, the deglitcher makes the glitch uniform, independent of code. 1111 1000 1000 0111 0000 ANALOG OUTPUT VOUT LSB MSB 0 20 Ultralow 1nV-s Glitch 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 1111 0001 0000 1111 0000 VREF (32,767/32,768) VREF (1/32,768) 0V –VREF (1/32,768) –VREF 1591/97 F02b Figure 7. With a dual op amp, the LTC1597 performs 4-quadrant multiplication. With a fixed 10V reference, it provides a ±10V bipolar output. For fast bipolar settling applications, an LT1468 can be used for the output amplifier. Linear Technology Magazine • February 1999 DESIGN FEATURES Bipolar ±10V Output with Two Op Amps 0.92LSB (140µV) at 17 bits for room temperature. The circuit uses the LTC1597 in its unipolar mode with the reference input inverted (–VREF, by means of R1 and R2 and an external op amp) for the output voltage range 0V to VREF. When the sign bit changes, the analog switch changes the reference input polarity to noninverting (VREF) for the output range 0V to –VREF. modes of operation. For AC signals less than 40kHz, the THD+noise is superb (better than 90dB) and is still very good out to 100kHz (78dB). Filtering at the output of the LT1468 is necessary to reduce the noise bandwidth to acceptable levels. The wider the bandwidth, the higher the noise floor. The LTC1597 contains all the 4-quadrant resistors necessary for bipolar operation. For a fixed 10V reference, the circuit shown in Figure 7 gives a precision –10V to 10V output swing, with a minimum of external components: a feedback capacitor and a dual op amp. The bipolar zero error is 8LSB maximum over temperature. If two LT1468 op amps are used instead of the LT1112, the circuit can perform wider bandwidth 4-quadrant multiplication, where the reference input is driven by a ±10V AC input signal and VOUT swings ±10V . Figure 6 shows a graph of the multiplying mode total harmonic distortion and noise of the LTC1597/LT1468 combination in both unipolar and bipolar 17-Bit Sign Magnitude DAC Gives Perfect Bipolar Zero Figure 8 shows a novel application of the LTC1597, a 17-bit sign magnitude DAC, and the resulting output coding. This circuit has an extremely accurate bipolar zero error, which is the offset voltage of the current-tovoltage op amp plus the bias current times the DAC feedback resistor. For the LT1468, this corresponds to a maximum bipolar zero error of 16 94dB SFDR Digital Sine Wave Generator Figure 9 shows the circuit diagram for a variable frequency digital waveform generator. The circuit shows the bipolar configuration for the LTC1597 but the unipolar configuration will work just as well. For a sampling frequency of 50kHz and an output sine wave frequency of 1kHz, the second harmonic distortion is –94dB and the third harmonic is –101dB. The on-chip deglitcher circuit minimizes the code-dependent glitch (which 14 15 Bipolar Sign Magnitude Code Table LTC203AC DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB SIGN MSB 1 2 15V LTC1236A-10 2 1111 0000 0000 0000 0000 1111 1 1 1 0 0 0 3 6 VREF ANALOG OUTPUT VOUT 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1111 0001 0000 0000 0001 1111 VREF (65,535/65,536) VREF (1/65,536) 0V 0V –VREF (1/65,536) –VREF (65,535/65,536) + 4 5V LT1468 – 0.1µF 15pF 3 R1 2 RCOM 1 REF 5 RFB 23 4 ROFS SIGN BIT 20pF R2 R1 ROFS RFB LTC1597 10 T0 21 24 TO 27 – 6 I0UT 16 DATA INPUTS 16-BIT DAC AGND 7 + LT1468 VOUT 22 DGND WR LD CLR 9 8 28 WR LD CLR Figure 8. This 17-bit sign-magnitude DAC uses the LTC1597 in its unipolar mode with the reference bit inverted (–VREF) for the output range 0V to VREF. When the sign bit changes, the analog switch changes the reference input polarity to noninverting (VREF) for the output range 0V to –VREF. The resulting circuit produces an impressive bipolar zero error of 140µV (0.92LSB) max at room temperature—less than 1LSB at 17 bits. Linear Technology Magazine • February 1999 21 DESIGN FEATURES 2 LTC1236A-10 15V 10V 6 + 4 5V LT1001 0.1µF – 3 R1 n = 24–32 BITS SERIAL OR PARALLEL DATA INPUT n 1 REF 5 RFB 23 4 ROFS 15pF n SERIAL OR BYTE LOAD REGISTER 2 RCOM R2 R1 ROFS RFB PHASE ACCUMULATOR PARALLEL n DELTA PHASE REGISTER M n Σ n PHASE REGISTER CLOCK FREQUENCY CONTROL PHASE TRUNCATION 16 BITS LTC1597 16-BIT DAC AGND 10 T0 21 24 TO 27 – 6 I0UT n SINE ROM 16 DATA LOOKUP INPUTS TABLE + 7 LOWPASS FILTER LT1468 22 fO = DGND M • fC 2n WR LD CLR 9 8 28 fC CLR Figure 9. This digital waveform generator produces a 1kHz sine wave with a second harmonic distortion of –94dB. The sampling frequency is 50kHz. BIPOLAR MODE DAC OUTPUT ERROR DAC OUTPUT ERROR UNIPOLAR MODE DAC TRANSFER CURVE WITH VOS IN CURRENT-TO-VOLTAGE OP AMP DAC TRANSFER CURVE WITH VOS IN CURRENT-TO-VOLTAGE OP AMP AND REF INVERTING OP AMP GAIN ERROR = 2VOSI-to-V + 4VOSINV GAIN ERROR = VOSI-to-V DAC TRANSFER CURVE WITH IDEAL OP AMP OFFSET ERROR = VOSI-to-V 0 NEGATIVE FULL-SCALE ERROR = 2VOSI-to-V 65,535 32,768 CODE BIPOLAR ZERO ERROR = 3VOSI-to-V + 2VOSINV DAC TRANSFER CURVE WITH IDEAL OP AMP 32,768 CODE 0 65,535 1720 G01 1720 G01 Figure 10. The effect of op amp offset on the LTC1597 gain and offset errors in unipolar mode (left) and bipolar mode (right); op amp offset has virtually no effect on DAC linearity; it merely shifts the end points. Table 1. Amplifiers recommended for use with the LTC1597, with relevant specifications Amplifier Specifications Amplifier VOS µV IB nA AOL V/mV Voltage Noise nV/ Hz LT1001 25 2 800 10 0.12 LT1097 50 0.35 1000 14 LT1112 (dual) 60 0.25 1500 LT1124 (dual) 70 20 LT1468 75 10 22 Gain Bandwidth Product MHz Power Dissipation mW 0.25 0.8 46 0.008 0.2 0.7 11 14 0.008 0.16 0.75 10.5/op amp 4000 2.7 0.3 4.5 12.5 69/op amp 5000 5 0.6 22 90 117 Current Noise Slew Rate pA/ Hz V/µs Linear Technology Magazine • February 1999 DESIGN FEATURES causes distortion) by making the glitch impulse both ultralow and uniform with code. Op Amp Selection Considerations A significant advantage of the LTC1597 is the ability to choose the I-to-V output op amp to optimize system accuracy, speed, power and cost. Table 1 shows a sampling of op amps and their relevant specifications for this application. The LTC1597 is designed to minimize the sensitivity of INL and DNL to op amp offset; this sensitivity has been greatly reduced compared to that of competing multiplying DACs. Figure 10 summarizes the effects of op amp offset for both modes of operation. Note that the bipolar LSB size is twice its unipolar counterpart. As Figure 10 shows, op amp offset has a minimal effect on DAC linearity; it merely shifts the end points. LT1611/LT1613, continued from page 13 The amplifier’s input bias current, which flows through the feedback resistor, adds to the output offset voltage. The amplifier’s finite DC openloop gain also degrades accuracy. The DAC gain error is inversely proportional to the open-loop gain and feedback factor of the op amp. In unipolar mode at full-scale the feedback factor is 0.5; for a 0.2LSB of gain error (REF = 10V) at 16 bits, the openloop amplifier gain should be greater than 650,000. The op amp’s input voltage and current noise also limit DC accuracy. Noise effects accuracy similarly to voltage and current offsets and adds in an RMS fashion. As with any precision application, and with wide bandwidth amplifiers in particular, the noise bandwidth should be minimized with a filter on the output of the op amp to maximize resolution. VIN 80 + SHDN 70 Wherever system requirements demand true 16-bit accuracy over temperature, the LTC1597 provides the best solution. The LTC1597 has outstanding 1LSB linearity over temperature, ultralow glitch impulse, on-chip 4-quadrant resistors, low power consumption, asynchronous clear and a versatile parallel interface.Combined with the LT1468 op amp, the LTC1597 provides the best in its class, 1.7µs settling time to 0.0015%, while maintaining superb DC linearity specifications. SW D1 L1B 15µH LT1611 68.1k SHDN VOUT –10V/60mA NFB GND 10k 65 + EFFICIENCY (%) 75 C1 22µF Conclusion: C2 0.22µF L1A 15µH VIN 3.6V–7V 85 Referring to Table 1, the LT1001 provides excellent DC precision, low noise and low power dissipation. The LT1468 provides the optimum solution for applications requiring DC precision, low noise and fast 16-bit settling. C3 6.8µF 60 55 50 0 50 100 150 200 250 LOAD CURRENT (mA) 300 350 1611 TA02 Figure 15. 12V supply at L1A increases efficiency to 81% and output current to 350mA. 85 VIN = 6.5V EFFICIENCY (%) 75 VIN = 3.6V (847) 956-0666 (803) 946-0362 1613 • TA01 (800) 441-2447 Figure 16. 4-Cell to –10V inverting converter delivers 75mA from a 4V input. LT1611 4-Cell to –10V Inverting Converter A –10V low noise output can be generated in a similar manner as the –5V circuit described above. Figure 16’s circuit can deliver –10V at up to 60mA from a 3.6V input. Efficiency, graphed in Figure 17, reaches a high of 78%. 80 70 L1: SUMIDA CL562-150 C1: AVX TAJB226M010 C2: X7R CERAMIC C3: AVX TAJA685M016 D1: MOTOROLA MBR0520 VIN = 5V 65 60 Conclusion 55 The flexibility of individually controlled outputs in multiple-supply applications can make several LT1611/ LT1613 converters attractive compared to a multiple-output flyback 50 0 25 50 75 100 LOAD CURRENT (mA) 125 150 1611 TA02 Figure 17. 4-cell to –10V converter efficiency Linear Technology Magazine • February 1999 design with one large switching regulator and a custom transformer. Changing an output voltage on a multiple output flyback requires changing the transformer turns ratio, hardly a simple task. Conversely, individual control of each output, using the multiple LT1611/LT1613 approach, provides for complete control of each output voltage as well as supply sequencing. The LT1611 and LT1613 SOT-23 switchers provide small, low noise solutions to power generation needs in tight spaces. 23