74LVQ273 OCTAL D-TYPE FLIP FLOP WITH CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74LVQ273MTR 74LVQ273TTR wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the CLOCK pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols July 2004 Rev. 5 1/13 74LVQ273 Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN No SYMBOL NAME AND FUNCTION 1 CLEAR 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 Q0 to Q7 Asynchronous Master Reset (Active LOW) Flip-Flop Outputs D0 to D7 Data Inputs CLOCK 10 20 GND VCC Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OUTPUT FUNCTION CLEAR D CLOCK Q L X X L H L L H H H H X Qn X : Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 CLEAR NO CHANGE 74LVQ273 Table 4: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 ± 20 V mA ± 20 mA IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Current ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL ± 50 mA ± 400 mA -65 to +150 °C 300 °C Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC Parameter Value Unit Supply Voltage (note 1) 2 to 3.6 V VI Input Voltage 0 to VCC V VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time VCC = 3.0V (note 2) 0 to VCC V -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V Table 6: DC Specifications Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage TA = 25°C VCC (V) Min. Typ. Max. 2.0 3.0 to 3.6 3.0 Value Low Level Output Voltage 3.0 -55 to 125°C Min. Min. 0.8 IO=-50 µA 2.9 IO=-12 mA 2.58 2.99 2.9 2.9 2.48 2.2 IO=50 µA 0.002 0.1 IO=12 mA 0 0.36 ICC IOLD IOHD Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) V 0.8 2.48 Unit Max. 2.0 0.8 IO=24 mA II Max. 2.0 IO=-24 mA VOL -40 to 85°C V V 2.2 0.1 0.1 0.44 0.44 0.55 0.55 V 3.6 VI = VCC or GND ± 0.1 ±1 ±1 µA 3.6 VI = VCC or GND 4 40 40 µA 3.6 VOLD = 0.8 V max 36 36 mA VOHD = 2 V min -25 -25 mA 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω 3/13 74LVQ273 Table 7: Dynamic Switching Characteristics Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Value TA = 25°C VCC (V) Min. 3.3 -0.8 3.3 Typ. Max. 0.4 0.8 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.5 2 V CL = 50 pF 3.3 0.8 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CK to Q tPHL tW tW ts th tREM fMAX tOSLH tOSHL Propagation Delay Time CLR to Q CLEAR Pulse Width CLOCK Pulse Width Setup Time D to CK, HIGH or LOW Hold Time D to CK, HIGH or LOW Recovery Time CLEAR to CLOCK Maximum Clock Frequency Output To Output Skew Time (note1, 2) VCC (V) Value TA = 25°C Min. Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Max. 2.7 7.3 12.0 14.0 16.0 3.3(*) 2.7 6.0 9.0 10.5 12.0 9.8 15.5 18.0 21.0 3.3(*) 2.7 8.6 12.5 14.5 16.5 5.0 2.5 5.0 5.0 3.3(*) 4.0 2.2 4.0 4.0 2.7 5.0 2.0 5.0 5.0 4.0 1.6 4.0 4.0 (*) 3.3 2.7 4.0 -0.4 4.0 5.0 (*) 3.0 -0.3 3.0 4.0 3.0 0.4 3.0 3.5 (*) 2.0 0.3 2.0 2.5 4.0 -0.1 4.0 4.5 (*) 3.3 2.7 3.0 0.0 3.0 3.5 60 150 50 50 3.3(*) 2.7 90 190 70 70 3.3 2.7 3.3 2.7 (*) 3.3 0.5 0.5 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns ns MHz 1.0 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 4/13 74LVQ273 Table 9: Capacitive Characteristics Test Condition Symbol Parameter TA = 25°C VCC (V) CIN Input Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 Value Min. fIN = 10MHz Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 5 pF 30 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop) Figure 4: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance) RL = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) 5/13 74LVQ273 Figure 5: Waveform - Propagation Delays, Setup And Hold Times Clock Pulse Width (f=1MHz; 50% duty cycle) Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) 6/13 74LVQ273 Figure 7: Waveform - Recovery Time, Clear Pulse Width (f=1MHz; 50% duty cycle) 7/13 74LVQ273 SO-20 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016022D 8/13 74LVQ273 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.0256 BSC 0.60 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 9/13 74LVQ273 Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 10/13 TYP 0.504 30.4 0.519 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 74LVQ273 Tape & Reel TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/13 74LVQ273 Table 10: Revision History Date Revision 29-Jul-2004 5 12/13 Description of Changes Ordering Codes Revision - pag. 1. 74LVQ273 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. 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