3.3V 32-1250Mbps AnyRate™ CLOCK AND DATA RECOVERY SY87701L DESCRIPTION FEATURES ■ Industrial temperature range (–40°C to +85°C) ■ 3.3V power supply ■ Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, etc. ■ Two on-chip PLLs: one for clock generation and another for clock recovery ■ Selectable reference frequencies ■ Differential PECL high-speed serial I/O ■ Line receiver input: No external buffering needed ■ Link fault indication ■ 100K ECL compatible I/O ■ Available in 28-pin SOIC and 32-pin EP-TQFP packages The SY87701L is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 1.25Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87701L also includes a link fault detection circuit. APPLICATIONS ■ ■ ■ ■ SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24 Fibre Channel, Escon Gigabit Ethernet/Fast Ethernet Proprietary architecture up to 1.25Gbps BLOCK DIAGRAM PLLR P/N RDINP (PECL) RDINN RDOUTP (PECL) PHASE DETECTOR RDOUTN RCLKP (PECL) 0 1 CHARGE PUMP VCO RCLKN PHASE/ FREQUENCY DETECTOR LINK FAULT DETECTOR CD (PECL) REFCLK (TTL) PHASE/ FREQUENCY DETECTOR CHARGE PUMP VCO 1 LFIN (TTL) TCLKP (PECL) 0 TCLKN VCC VCCA VCCO GND DIVIDER BY 8, 10, 16, 20 SY87701L DIVSEL 1/2 (TTL) FREQSEL 1/2/3 (TTL) PLLS P/N CLKSEL (TTL) AnyRate™ is a trademark of Micrel, Inc. Rev.: B 1 Amendment: /0 Issue Date: September 2000 Micrel SY87701L PIN CONFIGURATION 24 RDOUTN FREQSEL1 6 REFCLK 7 FREQSEL2 8 23 VCCO Top View SOIC Z28-1 FREQSEL3 9 22 RCLKP 21 RCLKN 20 VCCO N/C 10 19 TCLKP PLLSP 11 18 TCLKN PLLSN 12 17 CLKSEL RDINP 2 23 RDOUTN RDINN 3 22 VCCO FREQSEL1 4 REFCLK 5 FREQSEL2 6 19 VCCO FREQSEL3 7 18 TCLKP NC 8 17 TCLKN Top View EP-TQFP H32-1 9 21 RCLKP 20 RCLKN 10 11 12 13 14 15 16 CLKSEL PLLRP GND PLLRN GND 15 PLLRN 24 RDOUTP GNDA GND 14 1 PLLSN 16 PLLRP NC PLLSP GND 13 DIVSEL2 RDINN 5 CD 25 RDOUTP 31 30 29 28 27 26 25 VCC RDINP 4 32 VCC 26 DIVSEL2 VCCA 27 CD VCCA LFIN 2 DIVSEL1 3 LFIN 28 VCC DIVSEL1 VCCA 1 PIN DESCRIPTIONS INPUTS FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs. These inputs select the output clock frequency range as shown in the “Frequency Selection” Table. RDINP, RDINN [Serial Data Input] Differential PECL. These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of eight frequency ranges depending on the state of the FREQSEL pins. See “Frequency Selection” Table. DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs. These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency Selection” Table. REFCLK [Reference Clock] TTL input. This input is used as the reference for the internal frequency synthesizer and the “training” frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. CLKSEL [Clock Select] TTL Input. This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. CD [Carrier Detect] PECL Input. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to lock onto the clock frequency generated from REFCLK. OUTPUTS LFIN [Link Fault Indicator] TTL Output. This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. 2 Micrel SY87701L RDOUTP, RDOUTN [Receive Data Output] Differential PECL. These ECL 100K outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. PLLSP, PLLSN [Clock Synthesis PLL Loop Filter] External loop filter pins for the clock synthesis PLL. RCLKP, RCLKN [Clock Output] Differential PECL. These ECL 100K outputs represent the recovered clock used to sample the recovered data (RDOUT). POWER & GROUND PLLRP, PLLRN [Clock Recovery PLL Loop Filter] External loop filter pins for the receiver PLL. VCC VCCA VCCO GND NC TCLKP, TCLKN [Clock Output] Differential PECL. These ECL 100K outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). Supply Voltage(1) Analog Supply Voltage(1) Output Supply Voltage(1) Ground No Connect NOTE: 1. VCC, VCCA, VCCO must be the same value. FUNCTIONAL DESCRIPTION Lock Detect The SY87701L contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will pull the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30µs data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. 3 Micrel SY87701L CHARACTERISTICS Performance The SY87701L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. A Jitter Transfer (dB) Sinusoidal Input Jitter Amplitude (UI p-p) 0.1 15 -20dB/decade -20dB/decade 1.5 -20dB/decade Acceptable Range -20 0.40 f0 f1 f2 f4 ft fc Frequency Frequency OC/STS-N Level f0 (Hz) f1 (Hz) f2 (Hz) f3 (kHz) ft (kHz) OC/STS-N Level fc (kHz) P (dB) 3 10 30 300 6.5 65 3 130 0.1 12 10 30 300 25 250 12 225 0.1 Figure 1. Input Jitter Tolerance Figure 2. Jitter Transfer 4 Micrel SY87701L FREQUENCY SELECTION TABLE FREQSEL1 FREQSEL2 FREQSEL3 fVCO/fRCLK fRCLK Data Rates (Mbps) 0 0 0 1 750 – 1250 0 0 1 2 375 – 625 0 1 0 4 188 – 313 0 1 1 6 125 – 208 1 0 0 8 94 – 157 1 0 1 12 63 – 104 1 1 0 16 47 – 78 1 1 1 24 32 – 52 ABSOLUTE MAXIMUM RATINGS(1, 2) REFERENCE FREQUENCY SELECTION DIVSEL1 DIVSEL2 fRCLK/fREFCLK 0 0 8 VCC 0 1 10 1 0 16 1 1 LOOP FILTER Symbol COMPONENTS(1) R5 C3 PLLSP SONET Wide Range R5 = 80Ω C3 = 1.5µF (X7R Dielectric) R5 = 350Ω C3 = 0.47µF (X7R Dielectric) PLLRP Unit Power Supply –0.5 to +7.0 V VI Input Voltage –0.5 to VCC V IOUT Output Current –Continuous –Surge C4 PLLRN SONET Wide Range R6 = 50Ω C4 = 1.0µF (X7R Dielectric) R6 = 680Ω C4 = 0.47µF (X7R Dielectric) mA 50 100 Tstore Storage Temperature –65 to +150 °C TA Operating Temperature –40 to +85 °C θJA Thermal Resistance @still air 80 single layer board, 46 multi-layer °C/W NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. 2. Airflow of 500LFPM recommended. PLLSN R6 Value 20 Rating NOTE: 1. Suggested Values. Values may vary for different applications. 5 Micrel SY87701L DC ELECTRICAL CHARACTERISTICS Symbol Parameter Min. Typ. Max. Unit VCC Power Supply Voltage 3.15 3.3 3.45 V ICC Power Supply Current — 170 230 mA Condition PECL 100K DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C Symbol Parameter Min. Typ. Max. Unit V Condition VIH Input HIGH Voltage VCC - 1.165 — VCC - 0.880 VIL Input LOW Voltage VCC - 1.810 — VCC - 1.475 V IIL Input LOW Current 0.5 — — µA VIN = VIL(Min.) VOH Output HIGH Voltage VCC - 1.075 — VCC - 0.830 V 50Ω to VCC –2V VOL Output LOW Voltage VCC - 1.860 — VCC - 1.570 V 50Ω to VCC –2V Min. Typ. Max. Unit TTL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C Symbol Parameter Condition VIH Input HIGH Voltage 2.0 — VCC V VIL Input LOW Voltage — — 0.8 V IIH Input HIGH Current –175 — — — — +100 µA µA VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. IIL Input LOW Current –300 — — µA VIN = 0.5V, VCC = Max. VOH Output HIGH Voltage 2.0 — — V IOH = –0.4mA VOL Output LOW Voltage — — 0.5 V IOL = 4mA IOS Output Short Circuit Current 15 — 100 mA VOUT = 0V (maximum 1sec) AC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C Symbol Parameter Min. Typ. Max. Unit Condition fREFCLK * Byte Rate fVCO VCO Center Frequency 750 — 1250 MHz ∆fVCO VCO Center Frequency Tolerance — 5 — % tACQ Acquisition Lock Time — — 15 µs tCPWH REFCLK Pulse Width HIGH 4 — — ns tCPWL REFCLK Pulse Width LOW 4 — — ns tir REFCLK Input Rise Time — 0.5 2 ns tODC Output Duty Cycle (RCLK/TCLK) 45 — 55 % of UI tr, tf ECL Output Rise/Fall Time 100 — 500 ps tskew Recovered Clock Skew –200 — +200 ps tDV Data Valid 1/(2*fRCLK) – 200 — — ps tDH Data Hold 1/(2*fRCLK) – 200 — — ps 6 Nominal 50Ω to VCC –2 (20% to 80%) Micrel SY87701L TIMING WAVEFORMS tCPWL tCPWH REFCLK tODC tODC RCLK tSKEW tDV tDH RDOUT 7 Micrel SY87701L SW1 GND APPLICATION EXAMPLE GND VCC 1 2 3 4 5 (R17 - R22) 5kΩ x 6 6 R10 Q1 2N2222A LED D2 VCC Ferrite Bead BLM21A102 Stand Off R9 0.1µF VCC 1 VCC R1 2 LFIN R2 C1 RDIN R3 R4 DIVSEL2 26 4 RDINP RDOUTP 25 6 FREQSEL1 See Table 1 GND 80Ω LOOP FILTER NETWORK C3 C6 R7 0.1µF R8 C14 C15 VCCO 23 RCLKP 22 8 FREQSEL2 RCLKN 21 9 FREQSEL3 VCCO 20 10 N/C TCLKP 19 11 PLLSP TCLKN 18 12 PLLSN CLKSEL 17 0.1µF 0.1µF 0.1µF 0.1µF GND C18 C19 50Ω If VCC = +5V: R9 through R14 = 330Ω PLLRP 16 PLLRN 15 C16 C17 R6 14 GND REFCLK (TTL) C7 0.1µF RDOUTN 24 7 REFCLK 13 GND VCC 1N4148 J1 R5 1.5µF C8 DIODE D1 22µF CD 27 3 DIVSEL1 5 RDINN C2 C9 0.1µF VCC 28 C4 1.0µF R11 R12 R13 R14 R15 R16 Capacitor Pads (1206 format) VCCA FB1 22µF If VCC = +3.3V: R9 through R14 = 220Ω NC DPDT Slide Switch XTAL Oscillator 14 0.1µF 1 C5 Pin 1 (VCCA) C13 0.1µF 8 VCC VCC 7 C10 Pin 28 (VCC) 0.1µF 120Ω R23 C11 Pin 23 (VCCO) 0.1µF C12 Pin 20 (VCCO) 0.1µF For AC coupling only For DC mode only C1 = C2 = 0.1µF C1 = C2 = Shorted R1 = R2 = 680Ω R1 = R2 = 130Ω R3 = R4 = 1kΩ R3 = R4 = 82Ω NOTE: 1. C5 and C10–C12 are decoupling capacitors and should be kept as close to the power pins as possible. Table 1. 8 Micrel SY87701L Material List For Bypass and AC coupling capacitor, high quality factor (High Q) capacitors are recommended. This will optimize the performance of the device in high frequency domain. The suggested dielectric characteristics for these capacitors are NPO and/or COG. AVX is a suggested provider of electronic components. www.avxcorp.com Component Part No.(1, 2) Description SY87700L/SY87700V/SY87701L/SY87701V U1 80Ω PLLS+, R5 1.5µF PLLS–, C3 50Ω PLLR+, R6 1.0µF PLLR–, C4 5kΩ or 4.7kΩ Pull Up Resistor x 6, R17 – R22 330Ω or 220Ω (see schematic) Output Pull Down Resistor, R11 – R16 4.7KΩ Pull Up Resistor, R7 130Ω Pull Up Resistor, R9 12kΩ Pull Down Resistor, R8 12kΩ R10 120Ω R23 0.1µF AC Coupling Capacitors x 6, C1, C2, C14 – C19 Tantalum, 22µF, 16V Decoupling Capacitor, C6, C8 0.1µF Decoupling Capacitors x 7, C5, C7, C9 – C13 Murata BLM21A102F Ferrite Bead, FB1 1N4148 Diode, D1 Johnson SMAs, ID#142-0701-201 SMAs x 9 6-pin Dip switch SW1 DPDT Slide Switch LED NOTES: 1. For VCC = 3.3V R8 = 12kΩ; R = 130Ω 2. For VCC = 5.0V R8 = 24kΩ; R9 = 200Ω PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY87701LZI Z28-1 Industrial SY87701LHI H32-1* Industrial *Contact factory for availability. 9 Micrel SY87701L 28 LEAD SOIC .300" WIDE (Z28-1) Rev. 02 10 Micrel SY87701L 32 LEAD EPAD TQFP (DIE UP) (H32-1) Rev. 01 11 Micrel SY87701L MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 12