ETC S3076TT

®
DEVICE
SPECIFICATION
S3076
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
MULTI-RATE
SONET/SDH
CLOCK RECOVERY UNIT
BiCMOS PECL
CLOCK GENERATOR
FEATURES
•
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GENERAL DESCRIPTION
SiGe BiCMOS technology
Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer and
jitter generation
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps) (with FEC)
Fibre Channel (2125 Mbps) (with FEC)
OC-24 (1244.16 Mbps) (with FEC)
Gigabit Ethernet (1250 Mbps) (with FEC)
Fibre Channel (1062.5 Mbps) (with FEC)
OC-12 (622.08 Mbps) (with FEC)
OC-3 (155.52 Mbps) (with FEC) NRZ data
Selectable reference frequencies
19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
Gigabit Ethernet frequencies)
Lock detect—monitors frequency of
incoming data
Low-jitter serial interface
+3.3 V supply
Compact 48 pin TQFP TEP package
Typical power 620 mW
Available in Die form also
The function of the S3076 clock recovery unit is to
derive high speed timing signals for SONET/SDHbased equipment. The S3076 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3076 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ signal with FEC capability up to 8 bytes per 255-byte
block and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3076 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter converts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
16
OTX
ORX
S3057
S3057
16
October 23, 2000 / Revision A
16
S3076
16
S3076
ORX
OTX
Network Interface
Processor
Network Interface
Processor
Figure 1. System Block Diagram
1
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
S3076 OVERVIEW
The S3076 supports clock recovery for the OC-48,
Fibre Channel (2125 Mbps), OC-24, Gigabit
Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or
OC-3 data rate with FEC capabilty up to 8 bytes per
255-byte block. Differential serial data is input to the
chip at the specified rate, and clock recovery is performed on the incoming data stream. An external oscillator is required to minimize the PLL lock time, and
provide a stable output clock source in the absence of
serial input data. Retimed data and clock are output
from the S3076.
Suggested Interface Devices
Sumitomo
OC-48 Optical Receiver
AMCC S3057
OC-48 Transceiver
Figure 2. S3076 Functional Block Diagram
CAP 1,2
2
LOOP
FILTER
VCO
TESTOUT
REFCLKP/N
TESTCLK
RATESEL[1:0]
2
SERCLKOP/N
CLOCK
DIVIDER
REFSEL
REFCMP
TESTEN
LOCK
DETECTOR
LOCKDET
LCKREFN
RST
PHASE DETECTOR
SERDATOP/N
SDN
SERDATIP/N
BYPASS
2
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7 with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
S3076 FUNCTIONAL DESCRIPTION
The S3076 clock recovery device performs the clock
recovery function for SONET OC-48, Fibre Channel
(2125 Mbps), OC-24, Gigabit Ethernet, Fibre
Channel (1062.5 Mbps), OC-12 or OC-3 serial data
links with FEC capabilty up to 8 bytes per 255-byte
block. The chip extracts the clock from the serial data
inputs and provides retimed clock and data outputs.
A 155.52/19.44 MHz (156.25/19.53 MHz for Gigabit
Ethernet and 132.81/16.60 MHz for Fibre Channel)
reference clock is required for phase locked loop
start up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit is used to multiply this reference to the
nominal bit rate. The input data rate is selected by
the RATESEL inputs. (See Table 1.)
Clock Recovery
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.
Lock Detect
Clock recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same frequency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The S3076 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than that stated in
Table 7, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock frequency is determined to be within that stated in
Table 7, the PLL will be declared in lock and the lock
detect output will go active. The assertion of SDN will
also cause an out of lock condition.
The phase relationship between the edge transitions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Table 1. Data Rate Select
RATESEL0
RATESEL1
Operating Mode
REFCLK
Frequency
0
0
1
1
1
1
1
0
1
0
1
0
0
1
OC-3
OC-12
OC-24
OC-48
Gigabit Ethernet
Fibre Channel (1062.5 Mbps)
Fibre Channel (2125 Mbps)
155.52/19.44
155.52/19.44
155.52/19.44
155.52/19.44
156.25/19.53
132.81/16.60
132.81/16.60
Table 2. Reference Frequency Select
Reference Frequency for Data Rates with FEC Capability of X bytes per 255–Byte Block
(For OC-3/12/24/48 Rates Only)
REFSEL
X=0
X=3
X=4
X=5
X=6
X=7
X=8
0
19.44 MHz
19.99 MHz
20.65 MHz
20.83 MHz
1
155.52 MHz
159.91MHz 161.21 MHz 162.53 MHz 163.87 MHz 165.26 MHz
166.63 MHz
October 23, 2000 / Revision A
20.15 MHz
20.31 MHz
20.48 MHz
3
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
SONET JITTER CHARACTERISTICS
Figure 3. Input Jitter Tolerance Specification
Performance
The S3076 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958
document, when used as specified.
Sinusodal
Input Jitter
Amplitude
(UI p-p)
1.5
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB optical/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 4. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied.
15
0.15
f0
f2
f1
f3
ft
Frequency
OC/STS
Level
f0
(Hz)
f1
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
48
10
600
6000
100
1000
12
10
30
300
25
250
3
10
30
300
6.5
65
243
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 7. when
a serial data input with no jitter is presented to the
serial data inputs. (See Table 7.)
Figure 4. Jitter Transfer Specification
P
slope = -20 dB/decade
Jitter
Transfer
Acceptable
Range
fc
Frequency
OC/STS
Level1,2
fc
(kHz)
P
(dB)
48
2000
0.1
12
500
0.1
3
130
0.1
243
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
3. Not specified in GR-253 or G.958.
4
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
FIBRE CHANNEL
JITTER CHARACTERISTICS
Table 3. Input Jitter Tolerance Specification at
node αR
Parameters
Performance
The S3076 PLL complies with the jitter specifications
proposed for Fibre Channel equipment defined by the
fibre channel methodology for Jitter specification.
tRJ
Frequency Dependent
Jitter Tolerance
(637 kHz to ≥ 5 MHz)
Deterministic Jitter
Tolerance
(637 kHz – 531 MHz)
Random Jitter
(637 kHz – 531 MHz)
tTJ
Total Jitter
tFDJ
tDJ
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB optical/electrical power penalty. Fibre Channel input
jitter tolerance requirements are shown in
Table 3.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 4 when
a serial data input with no jitter is presented to the
serial data inputs.
Description
Min
Max
Units
0.10
–
UI p-p
0.38
–
UI p-p
0.22
–
UI p-p
0.70
–
UI p-p
Table 4. Total Jitter Generation Specification at
node αT
Parameters
Description
DJ
TJ
Min
Max
Units
Deterministic Jitter
0.08
UI p-p
Total Jitter
0.23
UI p-p
Figure 5. Fibre Channel System Node Definition
Componet Receiver Node = αR
αT = Component Transmitter Node
SYSTEM
STORAGE
SYSTEM
HOST ADAPTOR
SERDES
DISK DRIVE
SERDES
BACKPLANE
PBC
REPEAETERS
CABLES
CONNECTORS
October 23, 2000 / Revision A
5
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Table 5. Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin#
Description
SERDATIP
SERDATIN
Diff.
CML
I
3
2
Serial Data In. Clock is recovered from the transitions on these
inputs. Internally biased and terminated. (See Figure 10.)
LVTTL
I
46
Active High. Used to bypass the PLL. It allows transmission of data
input without clock recovery.
45
Signal Detect. Active Low. A single-ended 10K PECL input to be
driven by the external optical receiver module to indicate a loss of
received optical power. When SDN is inactive, the data on the Serial
Data In (SERDATIP/N) pins will be internally forced to a constant zero,
and the PLL will be forced to lock to the REFCLK inputs. When SDN
is active, data on the SERDATIP/N pins will be processed normally.
I
6
7
Reference Clock. 155.52/19.44 MHz (or equivalent Fibre Channel
or Gigabit Ethernet frequency) input used to establish the initial
operating frequency of the clock recovery PLL and also used as a
standby clock in the absence of data, during reset or when SDN is
inactive. Internally biased.
I
40
39
Loop Filter Capacitor. The external loop filter capacitor and resistors
are connected to these pins. (See Figure 14.)
BYPASS
SDN
Single
Ended
LVPECL
REFCLKP
REFCLKN
Internally
Biased
Diff.
LVPECL
CAP1
CAP2
I
LCKREFN
LVTTL
I
17
Lock to Reference. Active Low. When active, the serial clock output
will be forced to lock to the local reference clock input [REFCLK].
RATESEL0
RATESEL1
LVTTL
I
20
19
Rate Select. Selects the operating mode (See Table 1.)
TESTCLK
LVTTL
I
15
Test Clock. Test input signal used for production test. Connect to
Ground for normal operation. This input is internally pulled High.
REFSEL
LVTTL
I
18
Selects the reference frequency (See Table 2.)
RST
LVTTL
I
16
Reset Input. Active High. Resets lock detect circuit and VCO divideby-N circuit for production test.
TESTEN
LVTTL
I
47
Test Enable. Active High. Bypasses the VCO for production test.
Connect to Ground for normal operation. This input is internally
pulled High.
SERDATOP
SERDATON
Diff.
CML
O
28
27
Serial Data Out. This signal is the delayed version of the incoming
data stream (SERDATIP/N) updated on the falling edge of Serial
Clock Out (SERCLKOP/N).
SERCLKOP
SERCLKON
Diff.
CML
O
34
33
Serial Clock Out. This signal is phase aligned with Serial Data Out
(SERDATO). (See Figure 8.)
LVTTL
O
10
Lock Detect. Clock recovery indicator. Set high when the internal
clock recovery has locked onto the incoming data stream.
LOCKDET is an asynchronous output.
LOCKDET
6
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 5. Pin Assignment and Descriptions (Continued)
Pin Name
Level
TESTOUT
I/O
Pin#
Description
O
23
Test Output. Leave open for normal operation.
37
42
Analog power supply.
AVCC
+3.3 V
I
AGND
GND
I
38, 41, 43 Analog GND connection.
I
1, 5, 9,
21, 24,
Power Supply.
26, 29,
32, 35, 48
I
4, 8, 11,
12, 13,
14, 22,
Ground connection.
25, 30,
31, 36, 44
VCC
+3.3 V
GND
GND
Pad Assignment
Pad #
Pad Center
Pin Name
Pad #
Pad Center
Pin Name
1
(756.900, 72.425)
VCC
14
(3751.375, 868.900)
GND
2
(861.900, 72.425)
TESTOUT
15
(3751.375, 973.900)
LOCKDET
3
(966.900, 72.425)
GND
16
(3751.375, 1078.900)
VCC
4
(1806.900, 72.425)
VCC
17
(3751.375, 1603.900)
GND
5
(1911.900, 72.425)
RATESEL0
18
(3751.375, 1708.900)
REFCLKN
6
(2016.900, 72.425)
RATESEL1
19
(3751.375, 1813.900)
REFCLKP
7
(2121.900, 72.425)
REFSEL
20
(3751.375, 1918.900)
VCC
8
(2226.900, 72.425)
LCKREFN
21
(3751.375, 2758.900)
GND
9
(2331.900, 72.425)
RST
22
(3751.375, 2863.900)
SERDATIP
10
(2436.900, 72.425)
TESTCLK
23
(3751.375, 2968.900)
SERDATIN
11
(2541.900, 72.425)
GND
24
(3751.375, 3073.900)
VCC
12
(3171.900, 72.425)
GND
25
(3171.900, 3871.375)
VCC
13
(3751.375, 756.900)
GND
26
(3066.900, 3871.375)
TESTEN
October 23, 2000 / Revision A
7
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Table 5. Pin Assignment and Descriptions (Continued)
Pad Assignment (Continued)
8
Pad #
Pad Center
Pin Name
Pad #
Pad Center
Pin Name
27
(2961.900, 3871.375)
BYPASS
40
(651.900, 3871.375)
AVCC
28
(2856.900, 3871.375)
SDN
41
(72.425, 3287.900)
GND
29
(2751.900, 3871.375)
GND
42
(72.425, 3182.900)
VCC
30
(2436.925, 3871.375)
AGND
43
(72.425, 3077.900)
SERCLKOP
31
(2226.900, 3871.375)
AVCC
44
(72.425, 2972.900)
SERCLKON
32
(2121.900, 3871.375)
AVCC
45
(72.425, 2867.900)
VCC
33
(2016.900, 3871.375)
AGND
46
(72.425, 2762.900)
GND
34
(1911.900, 3871.375)
AGND
47
(72.425, 1610.400)
GND
35
(1386.900, 3871.375)
CAP1
48
(72.425, 1505.400)
VCC
36
(1281.900, 3871.375)
CAP2
49
(72.425, 1400.400)
SERDATOP
37
(966.900, 3871.375)
AGND
50
(72.425, 1295.400)
SERDATON
38
(861.900, 3871.375)
AGND
51
(72.425, 1190.400)
VCC
39
(756.900, 3871.375)
AVCC
52
(72.425, 1085.400)
GND
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
19
20
21
22
RATESEL0
VCC
11
12
RATESEL1
GND
GND
Top View
13
14
15
16
17
18
8
9
10
GND
GND
TESTCLK
VCC
LOCKDET
38
37
GND
VCC
SERCLKOP
31
30
SERCLKON
VCC
GND
GND
29
28
VCC
SERDATOP
27
26
25
SERDATON
VCC
GND
23
24
AGND
CAP1
CAP2
AGND
AVCC
40
39
AGND
AVCC
42
41
S3076
48 Pin TQFP/TEP
36
35
34
33
32
GND
TESTOUT
VCC
6
7
LCKREFN
REFSEL
5
RST
VCC
October 23, 2000 / Revision A
SDN
GND
3
4
REFCLKP
REFCLKN
GND
46
45
44
43
VCC
SERDATIN
SERDATIP
GND
1
2
48
47
VCC
TESTEN
BYPASS
Figure 6. S3076 48 Pin TQFP/TEP Pinout
9
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Figure 7. 48 Pin TQFP/TEP Package
TOP VIEW
Die Width – 156.7 mils
Die Length – 161.5 mils
Table 6. Thermal Management
10
Device
Package Max Power
Θja
S3076
850 mW
50˚ C/W
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 7. Performance Specifications
Parameter
VCO Operating Frequency
Min
Ty p
Max
Units
2.125
2.488
2.67
GHz
0.0038
0.005
UI (rms)
Data Output Jitter with VCO locked to
SERDATIP/N
OC-48
OC-24
Condition
rms jitter
Not specified in GR-253
OC-12
0.002
0.005
UI (rms)
rms jitter
OC-3
0.002
0.005
UI (rms)
rms jitter
+100
ppm
Reference Clock Frequency Tolerance
-100
Acquisition Lock Time (OC-48)
19.44 MHz REFCLK
155.52 MHz REFCLK
Reference Clock
Input Duty Cycle
1800
250
40
60
% of UI
1.5
ns
60
120
ps
450
600
770
ppm
220
300
390
ppm
Reference Clock Rise & Fall Times
CML Output Rise & Fall Times
Frequency difference at which the PLL
goes out of lock (REFCLK compared to the
divided down VCO clock)
Frequency difference at which the receive
PLL goes into lock (REFCLK compared to
the divided down VCO clock)
µsec
Minimum transition
density of 20%.
Guaranteed but not
tested.
With device already
powered up and valid
ref. clk.
20% to 80% of
amplitude.
20% to 80%, 50 Ω load,
1 pF cap.
tSU
OC-48/Fibre Channel (2125 Mbps)
OC-24/Fibre Channel (1062.5 Mbps)
OC-12
OC-3
100
250
500
2500
ps
See Figure 8.
ps
See Figure 8.
tH
OC-48/Fibre Channel (2125 Mbps)
OC-24/Fibre Channel (1062.5 Mbps)
OC-12
OC-3
October 23, 2000 / Revision A
100
250
500
2500
11
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Figure 8. Receiver Output Timing Diagram
50%
SERCLKOP
tSU
tH
SERDATOP/N
Note: Output propagation delay time of high speed CML outputs is the time in pico seconds from the cross-over point of the
reference signal to the cross-over point of the output.
Table 8. Jitter Tolerance Specifications
Parameter
Min
Typ
Max
Units Conditions
Jitter Tolerance
STS-48
0.4
0.5
UI
1 MHz < f < 5 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-12
0.4
0.6
UI
250 kHz < f < 5 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-3
0.4
0.8
UI
65 kHz < f < 1 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-24
Table 9. Gigabit Ethernet Jitter Specifications
Parameter
Min
tJ Total Input Jitter Tolerance
599
ps
As specified in IEEE 802.3z.
tDJ Deterministic Input Jitter
Tolerance
370
ps
As specified in IEEE 802.3z.
12
Typ
Max
Units Conditions
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 10. Recommended Operating Conditions
Parameter
Ambient Temperature Under Bias (Industrial)
Voltage on VCC with respect to GND
Min
Typ
-40
3.135
3.3
Max
Units
+85
˚C
3.465
V
Voltage on any LVTTL Input Pin
0
VCC
V
Voltage on any LVPECL Input Pin
0
VCC
V
187
245
mA
Typ
Max
Units
ICC Supply Current1
1. Outputs open.
Table 11. Absolute Maximum Ratings
Parameter
Min
Storage Temperature
-65
+150
˚C
Voltage on VCC with respect to GND
-0.5
3.465
V
Voltage on any LVTTL Input Pin
-0.5
VCC
V
0
VCC
V
LVTTL Output Sink Current
8
mA
LVTTL Output Source Current
8
mA
Voltage on any LVPECL Input Pin
Electrostatic Discharge (ESD) Ratings
The S3076 is rated to the following voltages based on the human body model:
1. All pins are rated 1500 Volts except pin # 24(VCC), 37(AVCC), 38(AGND), 41(AGND), 42(AVCC),
and 43(AGND). Pins 24, 37, 38, 41, 42, and 43 are rated at 100 volts.
Adherence to standards for ESD protection should be taken during the handling of the devices to
ensure that the devices are not damaged. The standards to be used are defined in ANSI standard
ANSI/ESD S20.20-1999, "Protection of Electrical and Electronic Parts, Assemblies and Equipment."
Contact your local FAE or sales representative for applicable ESD application notes.
October 23, 2000 / Revision A
13
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Table 12. CML Input DC Characteristics
Parameter
∆VINDIFF
∆VINSINGLE
RDIFF
Description
Min
Typ
Max
Units
Conditions
Differential Input Voltage Swing
300
1900
mV
See Figure 9.
Single-ended Input Voltage Swing
150
950
mV
See Figure 9.
Differential Input Resistance
80
100
120
Ω
Min
Typ
Table 13. CML Output DC Characteristics
Parameter
VOL
(Data)
VOH
(Data)
∆VOUTDIFF
(Data)
∆VOUTSINGLE
(Data)
VOL
(Clock)
VOH
(Clock)
∆VOUTDIFF
(Clock)
∆VOUTSINGLE
(Clock)
Description
CML Output Low Voltage
CML Output High Voltage
CML Serial Output Differential Voltage
Swing
CML Serial Output Single-ended
Voltage Swing
CML Output Low Voltage
CML Output High Voltage
CML Serial Output Differential Voltage
Swing
CML Serial Output Single-ended
Voltage Swing
Max
Units
VCC
-1.0
VCC
-0.35
VCC
-0.65
VCC
-0.2
800
1600
mV
400
80 0
mV
VCC
-1.5
VCC
-0.5
VCC
-0.85
VCC
-0.25
800
1800
mV
400
900
mV
Conditions
V
100 Ω line-to-line.
V
100 Ω line-to-line.
100 Ω line-to-line.
See Figure 9.
100 Ω line-to-line at
2.5 Gbps. See Figure 9.
V
100 Ω line-to-line.
V
100 Ω line-to-line.
100 Ω line-to-line.
See Figure 9.
100 Ω line-to-line at
2.5 GHz. See Figure 9.
Table 14. LVTTL Input/Output DC Characteristics
Parameter
Description
Min
Typ
Max
Unit
Conditions
VIH
Input High Voltage
2.0
3.465
V
TTL VCC = Max
VIL
Input Low Voltage
0.0
0.8
V
TTL VCC = Max
IIH
Input High Current
50
µA
VIN = 2.4 V
IIL
Input Low Current
-500
µA
VIN = 0.5 V
2. 4
V
VIH = Min
VIL = Max
IOH = -100 µA
V
VIH = Min
VIL = Max
IOL = 1.0 mA
VOH
Output High Voltage
VOL
Output Low Voltage
0.5
Note: All parameters are specified with respect to the source termination and ground with VTTL = Max. = 3.465 V.
14
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 15. Single Ended LVPECL Input DC Characteristics
Parameter
Description
Min
Typ
Max
Units
VCC
-2.00
VCC
-1.2
VCC
-1.4
VCC
-0.5
Input Low Current
-100
0
µA
Input High Current
+50
350
µA
VIL
Input Low Voltage
VIH
Input High Voltage
IIL
IIH
Conditions
V
V
Table 16. Internally Biased Differential LVPECL Input AC Characteristics
Parameter
Description
Min
Typ
Max
Units
Conditions
VIL
Input Low Voltage
VCC
-2.00
VCC
-1.4
V
VIH
Input High Voltage
VCC
-1.2
VCC
-0.5
V
IIL
Input Low Current
-300
0
µA
VIL = VCC -2
IIH
Input High Current
-50
100
µA
VIH = VCC -0.5
Differential Input Voltage Swing
300
1200
mV
See Figure 9.
Single-ended Input Voltage Swing
150
600
mV
See Figure 9.
∆VINDIFF
∆VINSINGLE
Figure 9. Differential Voltage Measurement
V(+)
VSWING
V(–)
V(+) – V(-)
VD = 2 X VSWING
0.0 V
Note: V(+) – V(-) is the algebraic difference of the input signals.
October 23, 2000 / Revision A
15
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Figure 10. +5 V Differential PECL Driver to S3076 Differential CML Input AC Coupled
Termination
+5 V
0.01 µF
Zo=50 Ω
Vcc -0.5 V
330 Ω
330 Ω
+3.3 V
100 Ω
0.01 µF
Zo=50 Ω
Vcc -0.5 V
S3076
SERDATIP/N
Figure 11. S3076 Differential CML Output to S3057/S3067 Terminations
+3.3 V
+3.3 V
Zo=50 Ω
Vcc -0.5
100 Ω
Zo=50 Ω
Vcc -0.5
S3076
SERDATOP/N
SERCLKOP/N
S3057/S3067
SERDATIP/N
SERCLKIP/N
Figure 12. +5 V Differential PECL Driver to S3076 Reference Clock Input AC Coupled
Termination
+5 V
0.01 µF
330 Ω
330 Ω
155 MHz
OSCILLATOR
16
0.01 µF
Vcc -0.5 V
Zo=50 Ω
+3.3 V
100 Ω
Zo=50 Ω
Vcc -0.5 V
S3076
REFCLKP/N
October 23, 2000 / Revision A
S3076
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 13. +3 V Differential LVPECL Driver to S3076 Reference Clock Input DC Coupled
Termination
+3 V
Vcc -0.5 V
Zo=50 Ω
150 Ω
150 Ω
+3.3 V
100 Ω
Zo=50 Ω
Vcc -0.5 V
155 MHz
OSCILLATOR/
155MCK from S3057
S3076
REFCLKP/N
Figure 14. Loop Filter Capacitor Connections
56 Ω
CAP1
10 µF
CAP2
56 Ω
S3076
October 23, 2000 / Revision A
17
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3076
Ordering Information
PREFIX
DEVICE
PACKAGE
S – Integrated Circuit
3076
TT – 48 Pin TQFP/TEP
DI – Die
XXXX
Device
XX
Package
O 900
D
E
CE
RT
1
IS
X
Prefix
IFI
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 • (800)755-2622 • Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 2000 Applied Micro Circuits Corporation
D53/R82
18
October 23, 2000 / Revision A