SY89850U Precision Low-Power LVPECL Line Driver/Receiver with Internal Termination General Description The SY89850U is a 2.5V/3.3V precision, high-speed, differential receiver capable of handling clocks up to 4GHz and data streams up to 3.2Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that allows users to interface to any differential signal (AC or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV LVPECL, with extremely fast rise/fall times guaranteed to be less than 160ps. The SY89850U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89850U is part of Micrel's high-speed, Precision Edge™ product line. All support documentation can be found on Micrel's web site at www.micrel.com. Typical Application Precision Edge™ Features • Guaranteed AC performance over temperature and supply voltage: – DC- to > 3.2Gbps data rate throughput – 4GHz clock fmax (typ.) – <280ps In-to-Out tpd – <160ps tr/tf • Low power: 50mW (2.5V typ.) • Ultra-low jitter design: – <1ps(rms) random jitter – <10ps(pp) deterministic jitter – <10ps(pp) total jitter (clock) • Unique input termination and VT pin accepts DCand AC-coupled inputs (CML, PECL, LVDS) • Typical 800mV (100k) LVPECL Output Swing • Power supply 2.5V ±5% or 3.3V ±10% • Industrial temperature range –40°C to +85°C • Available in ultra-small (2mm x 2mm) 8-pin MLF™ package Applications • Backplane buffering • OC-12 to OC-192 SONET/SDN clock/data distribution • All Gigabit Ethernet clock or data distribution • Fibre Channel distribution Markets • • • • LAN/WAN Enterprise Servers ATE Test and Measurement Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. February 2005 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Ordering Information(1) Part Number SY89850UMG SY89850UMGTR (2) Package Type Operating Range Package Marking Lead Finish MLF-8 Industrial 850U with Pb-Free bar-line indicator NiPdAu Pb-Free MLF-8 Industrial 850U with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for dice availability. Dice are guaranteed at TA = 25°C, DC Electrical Only. 2. Tape and Reel. Pin Configuration 8-Pin MLF™ (MLF-8) Pin Description Pin Number Pin Name 1, 4 IN, /IN Differential Input: This input pair is the signal to be buffered. These inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of this pair internally terminates to a VT pin through 50Ω. Note that this input will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details. 2 VT Input Termination Center-Tap: Each side of the differential input pair terminates to this pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 3 VREF-AC 5 GND, Exposed Pad 7, 6 Q, /Q Differential 100K LVPECL Output: This LVPECL output is the output of the device. Terminate through 50Ω to VCC–2V. See “Output Interface Applications” section. 8 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pin as possible. February 2005 Pin Function Reference Output Voltage: This output biases to VCC –1.2V. Connect to VT pin when AC-coupling the input. Bypass with 0.01µF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. See “Input Interface Applications” section. Ground: Ground pin and exposed pad must be connected to the same ground plane. 2 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .......................... –0.5V to +4.0V Input Voltage (VIN) .................................. –0.5V to VCC LVPECL Output Current (IOUT) ................................... Continuous..................................................50mA Surge ........................................................100mA Input Current .............................................................. Source or sink current on IN, /IN ..............±50mA Termination Current ................................................... Source or sink current on VT ..................±100mA Source or sink current on VREF–AC .....................±2mA Lead Temperature (soldering, 20sec.) ............. 260°C Storage Temperature (Ts) ...............–65°C to +150°C Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA)................ –40°C to +85°C Package Thermal Resistance(3) MLF™ (θJA) Still-Air ..................................................... 93°C/W MLF™ (ψJB) Junction-to-Board .................................... 60°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C, unless noted. Symbol Parameter VCC Power Supply ICC Power Supply Current RDIFF_IN Differential Input Resistance (IN-to-/IN) RIN Input Resistance (IN-to-VT), (/IN-to-VT) VIH Input High Voltage (IN, /IN) VIL Input Low Voltage (IN, /IN) VIN Input Voltage Swing (IN, /IN) VDIFF_IN Differential Input Voltage Swing |IN–/IN| VT_IN In-to-VT (IN, /IN) VREF–AC Output Reference Voltage Condition Min Typ Max Units 2.375 3.0 2.5 3.3 2.625 3.6 V V 20 30 mA 90 100 110 Ω 45 50 55 Ω VCC–1.6 VCC V 0 VIH–0.1 V See Figure 1a. 0.1 1.7 V See Figure 1b. 0.2 No load, max. VCC Note 5 VCC–1.3 V VCC–1.2 1.28 V VCC–1.1 V Notes: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIH (min) not lower than 1.2V. February 2005 3 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U LVPECL Output DC Electrical Characteristics(6) VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to +85°C; RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VCC Output High Voltage Q, /Q VCC –1.145 VCC –0.895 V VOL Output Low Voltage Q, /Q VCC –1.945 VCC –1.695 V VOUT Output Voltage Swing Q, /Q See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 1100 1600 mV Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. AC Electrical Characteristics(7) VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to +85°C; RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter fMAX Maximum Operating Frequency Condition Min NRZ Data VOUT ≥ 400mV tpd Propagation Delay IN-to-Q tpd Tempco Differential Propagation Delay Temperature Coefficient tJITTER Data Random Jitter (RJ) Deterministic Jitter (DJ) Clock Cycle-to-Cycle Jitter Total Jitter (TJ) tr, tf Rise/Fall Time (20% to 80%) Q, /Q Typ Units Gbps Clock VIN ≥ 100mV Max 3.2 4 180 260 GHz 360 115 ps fs/°C Note 8 1 ps(rms) Note 9 10 ps(pp) Note 10 1 ps(rms) Note 11 10 ps(pp) 160 ps At full output swing. 50 100 Notes: 7. The circuit is designed to meet the AC specifications shown in the above table after thermal equilibrium has been established. 8. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps and 3.2Gbps. 9. Deterministic jitter is measured at 2.5Gbps and 3.2Gbps, with both K28.5 and 2 –1 PRBS pattern. 23 10. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn –Tn-1 where T is the time between rising edges of the output signal. 12 11. Total jitter definition: with an ideal clock input of frequency < fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. February 2005 4 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Single-Ended and Differential Swings Figure 1a. Singled-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagram February 2005 5 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Typical Operating Characteristics VCC = 3.3V, GND = 0V, VIN = ≥ 400mVpp, tr/tf ≤ 300ps, TA = 25°C, unless otherwise stated. February 2005 6 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Functional Characteristics VCC = 3.3V, GND = 0V, VIN = ≥ 400mVpp, tr/tf ≤ 300ps, TA = 25°C, unless otherwise stated. February 2005 7 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Input and Output Stages Figure 2b. Simplified LVPECL Output Stage Figure 2a. Simplified Differential Input Stage Input Interface Applications Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface (DC-Coupled) February 2005 8 Figure 3c. CML Interface (DC-Coupled) M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Output Interface Applications LVPECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω and 100Ω-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel TerminationThevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single- ended outputs must be terminated, or balanced. Note: 1. For +2.5V systems, R1 = 250Ω, R2 = 62.5Ω. Figure 4a. Parallel Termination-Thevenin Equivalent Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. 4. For 2.5V systems, Rb = 19Ω. Figure 4b. Parallel Termination (3-Resistor) Related Product and Support Documentation Part Number Function Data Sheet Link SY58601U Ultra-Precision Differential 800mV LVPECL Line Driver/Receiver with Internal Termination www.micrel.com/product-info/products/sy58601u.shtml MLFTM Application Note www.amkor.com/products/notes_papers/MLF_AppNote.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml HBW Solutions February 2005 9 M9999-020305 [email protected] or (408) 955-1690 Micrel, Inc. SY89850U Package Information 8-Pin Ultra-Small EPAD MLF™ (MLF-8) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. February 2005 10 M9999-020305 [email protected] or (408) 955-1690