SY89852U Precision Low Power Differential 2:1 LVPECL MUX with Internal Termination General Description The SY89852U is a 2.5V/3.3V precision, highspeed, 2:1 differential MUX capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. The differential input includes Micrel’s unique, patent pending 3-pin input termination architecture that allows users to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The unique, patent input isolation design minimizes crosstalk minimizing crosstalk induced jitter. The outputs are 800mV LVPECL, with extremely fast rise/fall time guaranteed to be less than 180ps. The SY89852U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89852U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at: www.micrel.com. Typical Applications ® Precision Edge Features • • • • • • • • • • • Provides a low jitter copy of the selected input Superior alternative to the EP58 2:1 MUX Low power: 58mW (2.5V nominal, no load) Guaranteed AC performance over temperature and supply voltage: – DC- to > 2.5Gbps data rate throughput – DC- to > 2.5GHz clock fMAX – < 340ps In-to-Out tpd – < 180ps tr/tf time Ultra-low Jitter Design: – <1ps(rms) random jitter – <10ps(pp) deterministic jitter – <10ps(pp) total jitter (clock) – <0.7ps(rms) crosstalk induced jitter Unique, patent-pending input isolation design minimizes crosstalk Unique, patent pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS) Typical 800mV (100k) LVPECL output swing Power supply 2.5V +5% or 3.3V +10% Industrial temperature range –40oC to +85oC Available in ultra-small (3mm x 3mm) 16-pin MLF® package Applications • • • • Redundant clock distribution SONET/SDH clock/data distribution Loopback Fibre Channel distribution Markets • • • • LAN/WAN Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. February 2007 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89852UMG MLF-16 Industrial 852U with bar-line designator NiPdAu Pb-Free SY89852UMGTR(2) MLF-16 Industrial 852U with bar-line designator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electrical Only. 2. Tape and Reel. Pin Configuration 16-Pin MLF® February 2007 2 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Pin Description Pin Number Pin Name Pin Function IN, /IN Differential Input: This input pair is the signal to be buffered. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of this pair internally terminates to a VT pin through 50Ω. Note that this input will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details. 16,5 VT Input Termination Center-Tap: Each side of the differential input pair terminates to this pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 8,13 VCC Positive Power Supply. Bypass with 0.1µF⎪⎪0.01µF low ESR capacitors as close to the VCC pin as possible. 12,9 Q, /Q Differential 100K LVPECL Output: This LVPECL output is the output of the device. Terminate through 50Ω to VCC –2V. PECL output requires DC path to ground. Thus, AC-coupled applications require pull-down resistors. See “Output Interface Applications” section. 10,11,14,15 GND, Exposed Pad Ground. Ground pin and exposed pad must be connected to the same ground plane. 6 SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25KΩ pull-up resistor and will default to a logic HIGH state if left open. 7 NC No connect. 1,2, 3,4 Truth Table IN0 IN1 SEL(1) Q 0 X 0 0 1 X 0 1 X 0 1 0 X 1 1 1 Note: 1. SEL is connected to a 25kΩ pull-up resistor and will default to logic high if left open. Functional Block Diagram February 2007 3 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ..........................–0.5V to +4.0V Input Voltage (VIN) ..................................–0.5V to VCC LVPECL Output Current (IOUT) Continuous ................................................. 50mA Surge........................................................ 100mA Termination Current(3) Source or sink current on VT .................... ±50mA Lead Temperature (soldering, 20sec.) ...........+260°C Storage Temperature (Ts)..................–65°C to 150°C Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA)................ –40°C to +85°C Package Thermal Resistance(4) MLF® (θJA) Still-Air ..................................................... 60°C/W MLF® (ψJB) Junction-to-Board .................................... 38°C/W DC Electrical Characteristics(5) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCC Power Supply Condition Min Typ Max Units 2.375 2.5 2.625 V 3.0 3.3 3.6 V 23 35 mA ICC Power Supply Current No load, max. VCC RDIFF_IN Differential Input Resistance (IN-to-/IN) 80 100 120 Ω RIN Input Resistance (IN-to-VT) 40 50 60 Ω VIH Input High Voltage (IN-to-/IN) VCC –1.2 VCC V VIL Input Low Voltage (IN-to-/IN) 0 VIH–0.1 V VIN Input Voltage Swing (IN-to-/IN) See Figure 1a. 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing |IN-/IN| See Figure 1b. VT_IN IN-to-VT (IN-to-/IN) 0.2 V 1.28 V Notes: 1. Permanent device damage may occur if the “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability, use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ψJB use a 4-layer board in still air, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2007 4 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U LVPECL Outputs DC Electrical Characteristics(7) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C; RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage Q, /Q VCC–1.145 VCC–0.895 V VOL Output LOW Voltage Q, /Q VCC–1.945 VCC–1.695 V VOUT Output Voltage Swing Q, /Q See Figure 1a. 550 800 mV VDIFF-OUT Differential Output Voltage Swing Q,/Q See Figure 1b. 1100 1600 mV Min Typ LVTTL/CMOS DC Electrical Characteristics(7) Symbol Parameter Condition VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 IIH Input HIGH Current -125 IIL Input LOW Current -300 Max Units VCC V 0.8 V 30 µA µA Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. February 2007 5 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U AC Electrical Characteristics(8) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, RL = 50Ω to VCC –2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Operating Frequency NRZ Data 2.5 3.2 Gbps Clock, VOUT ≥ 400mV 2.5 3.5 GHz VIN ≥ 100mV 140 100 230 250 Propagation Delay tPD tPD Tempco IN-to-Q, /IN-to-Q SEL-to-Q Differential Propagation Delay Temperature Coefficient 340 400 ps ps fs/oC 100 Data tJitter Random Jitter (RJ) Note 9 1 psRMS Deterministic Jitter (DJ) Note 10 10 psRMS Note 11 1 psPP Clock Cycle-to-Cycle Jitter tr, tf Total Jitter Note 12 10 psRMS Crosstalk-induced Jitter Note 13 0.7 psRMS 180 ps Output Rise/Fall Time (20% to 80%) At full output swing. 50 100 Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps. 23 10. DJ is measured at 2.5Gbps, with both K28.5 and 2 – 1 PRBS pattern. 11. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the output signal. 12 12. Total jitter definition: With an ideal clock input of frequency <fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 13. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs. February 2007 6 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Operating Characteristics VCC = 2.5V, VIN = 100mV, TA = 25°C; unless otherwise stated. Amplitude vs. Frequency Propagation Delay vs. Temperature PROPAGATION DELAY (ps) 900 AMPLITUDE (mV) 800 700 600 500 400 300 7000 6000 5000 4000 3000 2000 0 100 1000 200 214 212 IN1 to Q 210 208 206 204 IN0 to Q 202 200 198 196 194 192 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FREQUENCY (MHz) February 2007 7 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Operating Characteristics February 2007 8 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Singled-Ended and Differential Swings Figure 1b. Differential Voltage Swing Figure 1a. Single-Ended Voltage Swing Timing Diagrams Figure 2. Timing Diagram February 2007 9 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Input and Output Stages Figure 3a. Simplified Differential Input Stage February 2007 Figure 3b. Simplified LVPECL Output Stage 10 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Input Interface Applications Option: may connect VT to VCC Figure 4a. LVPECL Interface (DC-Coupled) Figure 4b. LVPECL Interface (AC-Coupled) Figure 4d. CML Interface (AC-Coupled) Figure 4e. LVDS Interface February 2007 11 Figure 4c. CML Interface (DC-Coupled) M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Output Interface Applications Note: For +2.5V systems: Rb = 19Ω For 3.3V systems Rb = 50Ω Note: For +2.5V systems R1 = 250Ω, R2 = 82.5Ω Figure 5a. Parallel Thevenin-Equivalent Termination Figure 5b. Parallel Termination (3-Resistor) Note: For +2.5V systems: Rb = 50Ω For 3.3V systems Rb = 100Ω The output pair requires a DC-current path to GND. Figure 5c. AC-Coupled Output Pull-down Resistors Related Product and Support Documentation Part Number Function Data Sheet Link SY89852U Precision Low Power Differential 2:1 LVPECL MUX w/Internal Termination www.micrel.com/product-info/products/sy89852u.shtml MLF® Application Note www.amkor.com/products/notes_papers/MLF_AppNote.pdf New Products and Applications www.micrel.com/product-info/products/solutions.shtml HBW Solutions February 2007 12 M9999-021307-B [email protected] or (408) 955-1690 Micrel, Inc. SY89852U Package Information 16-Pin (3mm x 3mm) MLF® (MLF-16) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2004 Micrel, Incorporated. February 2007 13 M9999-021307-B [email protected] or (408) 955-1690