FAIRCHILD FDH20N40

FDH20N40 / FDP20N40
20A, 400V, 0.216 Ohm, N-Channel SMPS Power MOSFET
Applications
Features
Switch Mode Power Supplies(SMPS), such as
• Low Gate Charge
Requirement
• PFC Boost
Qg
results
in
Simple
Drive
• Improved Gate, Avalanche and High Reapplied dv/dt
Ruggedness
• Two-Switch Forward Converter
• Single Switch Forward Converter
• Flyback Converter
• Reduced rDS(ON)
• Buck Converter
• Reduced Miller Capacitance and Low Input Capacitance
• High Speed Switching
• Improved Switching Speed with Low EMI
• 175°C Rated Junction Temperature
Package
Symbol
JEDEC TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
D
SOURCE
DRAIN
GATE
G
DRAIN
(FLANGE)
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Parameter
Drain to Source Voltage
VGS
Gate to Source Voltage
Ratings
400
Units
V
±30
V
20
A
Drain Current
Continuous (TC = 25oC, VGS = 10V)
ID
Continuous (TC =
100oC,
VGS = 10V)
Pulsed (Note 1)
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Soldering Temperature for 10 seconds
Mounting Torque, 8-32 or M3 Screw
14
A
80
A
273
1.82
W
W/oC
-55 to 175
o
C
300 (1.6mm from case)
o
C
10ibf*in (1.1N*m)
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case
0.55
o
RθCS
Thermal Resistance Case to Sink, Flat, Greased Surface
0.24
oC/W
RθJA
Thermal Resistance Junction to Ambient (TO-247)
40
o
RθJA
Thermal Resistance Junction to Ambient (TO-220)
62
o
©2002 Fairchild Semiconductor Corporation
C/W
C/W
C/W
FDH20N40 / FDP20N40 Rev. A,
FDH20N40 / FDP20N40
October 2002
Device Marking
FDH20N40
Device
FDH20N40
Package
TO-247
Reel Size
Tube
Tape Width
-
Quantity
30
FDP20N40
FDP20N40
TO-220
Tube
-
50
Electrical Characteristics TC = 25°C (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
400
-
-
V
-
0.43
-
Statics
BVDSS
Drain to Source Breakdown Voltage
∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient
ID = 250µA, VGS = 0V
V/°C Reference to 25°C
ID = 1mA
rDS(ON)
Drain to Source On-Resistance
VGS = 10V, ID = 10A
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250µA
-
0.200
0.216
Ω
2.0
3.5
4.0
V
VDS = 400V
TC = 25oC
-
-
25
VGS = 0V
TC =150oC
-
-
250
-
±100
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
VGS = ±20V
-
VDS = 50V, ID = 10A
10
-
-
S
VGS = 10V
VDS = 320V
ID = 20A
-
35
42
nC
-
10
12
nC
-
12
14.4
nC
VDD = 200V
ID = 20A
RG = 10Ω
RD = 15.4Ω
-
12.4
-
ns
-
32.5
-
ns
-
30
-
ns
-
34
-
ns
-
1840
-
pF
µA
nA
Dynamics
gfs
Forward Transconductance
Qg(TOT)
Total Gate Charge at 10V
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
td(ON)
Turn-On Delay Time
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
Fall Time
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25V, VGS = 0V
f = 1MHz
-
245
-
pF
-
18
-
pF
1100
-
-
mJ
-
-
20
A
-
-
20
A
-
-
80
A
Avalanche Characteristics
EAS
Single Pulse Avalanche Energy (Note 2)
IAR
Avalanche Current
Drain-Source Diode Characteristics
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
showing the
integral reverse
p-n junction diode.
D
G
ISM
Pulsed Source Current (Note 1)
(Body Diode)
VSD
Source to Drain Diode Voltage
ISD = 20A
-
0.9
1.2
V
Reverse Recovery Time
ISD = 20A, dISD/dt = 100A/µs
-
351
456
ns
Reverse Recovered Charge
ISD = 20A, dISD/dt = 100A/µs
-
4.5
5.85
µC
trr
QRR
S
Notes:
1: Repetitive rating; pulse width limited by maximum junction temperature
2: Starting TJ = 25°C, L = 5.5mH, IAS = 20A
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A
FDH20N40 / FDP20N40
Package Marking and Ordering Information
FDH20N40 / FDP20N40
Typical Characteristics
100
TC = 25oC
VGS DESCENDING
ID, DRAIN TO SOURCE CURRENT (A)
ID, DRAIN TO SOURCE CURRENT (A)
100
10V
7V
6.5V
6V
5.5V
10 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1
1
10
TC = 175oC
VGS DESCENDING
10V
7V
6.5V
6V
5.5V
10 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1
1
100
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 2. Output Characteristics
40
ID , DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 50V
30
20
TJ = 25oC
10
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
Figure 1. Output Characteristics
TJ = 175oC
100
3.0
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
VGS = 10V, ID = 10A
0.0
-50
-25
0
25
50
75
100
125
150
175
o
VGS , GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE ( C)
Figure 3. Transfer Characteristics
Figure 4. Normalized Drain To Source On
Resistance vs Junction Temperatrue
CISS
1000
C, CAPACITANCE (pF)
VGS , GATE TO SOURCE VOLTAGE (V)
15
COSS
100
10
CRSS
VGS = 0V, f = 1MHz
1
1
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Capacitance vs Drain To Source Voltage
©2002 Fairchild Semiconductor Corporation
ID = 20A
200V
10
320V
80V
5
0
0
10
20
30
40
50
60
Qg, GATE CHARGE (nC)
Figure 6. Gate Charge Waveforms For Constant
Gate Current
FDH20N40 / FDP20N40 Rev. A
35
ID, DRAIN CURRENT (A)
ISD , SOURCE TO DRAIN CURRENT (A)
100
40
30
25
20
15
10
TJ = 175oC
TJ = 25oC
100µs
10
OPERATION IN THIS AREA
LIMITED BY RDS(ON)
10ms
1
DC
5
0
0.2
1ms
TC = 25oC
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
1
1.0
VSD , SOURCE TO DRAIN VOLTAGE (V)
10
100
1000
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Source to Drain Diode Forward Voltage
Figure 8. Maximum Safe Operating Area
ID, DRAIN CURRENT (A)
20
15
10
5
0
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (°C)
ZθJC , NORMALIZED THERMAL IMPEDANCE
Figure 9. Maximum Drain Current vs Case Temperature
2.0
1.0
0.50
0.20
0.1
t1
0.10
PD
0.05
t2
0.02
0.01
0.01
10-5
DUTY FACTOR, D = t1 / t2
PEAK TJ = (PD X ZθJC X RθJC) + TC
SINGLE PULSE
10-4
10-3
10-2
10-1
100
t1 , RECTANGULAR PULSE DURATION (s)
Figure 10. Normalized Maximum Transient Thermal Impedance
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A
FDH20N40 / FDP20N40
Typical Characteristics
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 11. Unclamped Energy Test Circuit
Figure 12. Unclamped Energy Waveforms
VDS
Qg(TOT)
RL
VDS
VGS
VGS = 10V
+
VDD
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 13. Gate Charge Test Circuit
Figure 14. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 15. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 16. Switching Time Waveform
FDH20N40 / FDP20N40 Rev. A
FDH20N40 / FDP20N40
Test Circuits and Waveforms
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
FACT™
ActiveArray™
FACT Quiet Series™
Bottomless™
FASTâ
CoolFET™
FASTr™
CROSSVOLT™ FRFET™
DOME™
GlobalOptoisolator™
EcoSPARK™
GTO™
E2CMOSTM
HiSeC™
EnSignaTM
I2C™
Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™
ImpliedDisconnect™ PACMAN™
POP™
ISOPLANAR™
Power247™
LittleFET™
PowerTrenchâ
MicroFET™
QFET™
MicroPak™
QS™
MICROWIRE™
QT Optoelectronics™
MSX™
Quiet Series™
MSXPro™
RapidConfigure™
OCX™
RapidConnect™
OCXPro™
SILENT SWITCHERâ
OPTOLOGICâ
SMART START™
OPTOPLANAR™
SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFETâ
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I1