REJ03F0263-0100 Rev. 1.00 Jan. 24. 2008 R8A66162SP 32-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH DESCRIPTION The R8A66162SP is a semiconductor integrated circuit for LED array driver with 32-bit serial-input, parallel output shift register, equipped with direct set input and output latches. The R8A66162SP guarantees sufficient 24mA (Vcc=5.0V case) output current to drive anode common LED, allowing 32-bit simultaneous and continuous current output. The parallel outputs are open-drain outputs. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. R8A66162SP is the succession product of M66313FP. FEATURES ● Anode common LED drive ● VCC 5V or 3.3V single power supply ● High output current: All parallel outputs Q1~Q32 IOL=24mA (at VCC=5.0V), IOL=12mA (at VCC=3.3V), LEDs can be turned on simultaneously. ● Low power dissipation: 200uW/package (max) (VCC=5.0V, Ta=25OC, quiescent state) ● High noise margin: Employment of Schmitt-trigger circuit on all inputs allows application with long wiring. ● Direct set input (SD) ● Open-drain output (Q1~Q32) ● Serial data output for cascading (SQ32) ● Wide operating temperature range (Ta=-40oC~+85oC) ● Pin configuration for easy layout on PCB. (Pin configuration allows easy cascade connection or LED connection) APPLICATION ● LED array drive, The various LED display modules ● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipments BLOCK DIAGRAM LOGIC DIAGRAM PARALLEL DATA OUTPUTS SERIAL DATA OUTPUT Q3 Q4 3 4 5 0 0 LE D S LE D S 0 LE D S 0 LE D S 0 LE D S 0 LE D S 0 LE D S 0 LE D S 1 1 1 1 1 1 1 1 CK D S CK D S CK D S CK D S CK D S CK D S CK D S CK D S OE A OUTPUT SERIAL ENABLE DATA INPUT INPUT DATA SIGNAL OE SIGNAL PARALLEL DATA OUTPUTS SERIAL DATA OUTPUT Q1∼Q32 SQ32 OUTPUT FORMAT REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 1 of 7 17 21 22 23 14 13 12 CK Vcc 9 15 37 S 10 SQ32 20 S 11 Q29 Q30 Q31 Q32 S S Q2 2 S Q1 1 8 16 24 30 36 43 SD LE GND SHIFT DIRECT LATCH CLOCK SET ENABLE INPUT INPUT INPUT R8A66162SP PIN CONFIGURATION ( TOP VIEW ) PARALLEL DATA OUTPUTS SERIAL DATA INPUT OUTPUT ENABLE INPUT LATCH ENABLE INPUT DIRECT SET INPUT SHIFT CLOCK INPUT SERIAL DATA OUTPUT PARALLEL DATA OUTPUTS GND Q1 Q2 Q3 Q4 Q5 Q6 GND VCC A OE LE SD CK VCC GND SQ32 Q27 Q28 Q29 Q30 Q31 Q32 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 Q7 Q8 Q9 Q10 Q11 GND Q12 Q13 Q14 Q15 Q16 VCC GND Q17 Q18 Q19 Q20 Q21 GND Q22 Q23 Q24 Q25 Q26 PARALLEL DATA OUTPUTS PARALLEL DATA OUTPUTS PARALLEL DATA OUTPUTS PARALLEL DATA OUTPUTS FUNCTIONAL DESCRIPTION The employment of silicon gate CMOS process of the R8A66162SP guarantees low power dissipation and maintains high noise margin as well as high output current and high speed required to drive LEDs. Each shift register bit consists of a flip-flop for shifting and an output latch. The shift operation takes place when the shift clock input CK changes from low-level to high-level. The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is shifted in sequence when a pulse is applied to CK. If the latch-enable input LE is turned high-level, the content of the shift register at that instant is latched. The parallel data outputs Q1~Q32 are open-drain outputs. To expand the number of bits, use the serial data output SQ32 which shows the output of the shift register of the 32nd bit. If the direct set input SD is turned low-level, Q1~Q32 and SQ32 are set. Then shift register and latches are set. If the high-level input is applied to the output enable input OE, Q1~Q32 are set to the high-impedance state, but SQ32 is not set to the high-impedance state. The shift operation is not affected when OE is changed. REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 2 of 7 R8A66162SP FUNCTION TABLE (Note: 1) SERIAL OUTPUT INPUT OPERATION MODE PARALLEL OUTPU TS SD CK LE A OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 L X X L L L L L H ↑ L H L L Q 01 Q 02 Q03 Q04 Q05 Q06 Q 07 Q08 Q 09 Q 010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q 020 Q 021 Q022 Q023 Q024 Q025 Q 026 Q027 Q028 Q 029 Q 030 Q031 q 031 H ↑ L L L Z Q 01 Q02 Q 03 Q04 Q 05 Q06 Q07 Q08 Q09 Q 010 Q011 Q012 Q013 Q014 Q015 Q016 Q017 Q018 Q019 Q 020 Q 021 Q022 Q023 Q024 Q025 Q 026 Q027 Q028 Q 029 Q 030 Q031 q0 31 H X H X L Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 9 Q 10 Q 11 Q 12 Q 13 Q 14 Q 15 Q 16 Q 17 Q 18 Q 19 Q 20 Q 21 Q 22 Q 23 Q 24 Q 25 Q 26 Q 27 Q 28 Q 29 Q 30 Q 31 Q 32 q 32 OUTPUT DISX ABLE X X X H Z q 32 SET X L L L L L L L L L L L L L L L L L L L L L L L L L L L L SQ32 H SHIFT LATCH 0 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 0 Z Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z Note 1. ↑ ：Transition from low-to-high-level 0 Q ：Shows the status of output Q before CK input changes X ：Irrelevant q 0 ：The content of shif t register before CK changes q ：The content of shif t register Z ：High-impedance state o ABSOLUTE MAXIMUM RATINGS (Ta=-40~85 C, unless otherwise noted) Symbol Vcc VI VO IO Parameter Supply voltage Input voltage Output voltage Output current per output pin Icc Pd Supply/GND current Power dissipation Storage temperature range Tstg Conditions Q1~Q32 SQ32 Vcc, GND Ratings -0.5~+7.0 -0.5~Vcc+0.5 -0.5~Vcc+0.5 50 ±25 -920, +20 650 -65~150 Unit V V V mA mA mW o C o RECOMMENDED OPERATING CONDITIONS (Ta=-40~85 C, unless otherwise noted) Parameter Symbol Vcc Supply voltage VI VO Topr Input voltage Output voltage Operating temperature range 5.0V support 3.3V support REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 3 of 7 Min. 4.5 3.0 0 0 -40 Limits Typ. 5.0 3.3 Unit Max. 5.5 3.6 Vcc Vcc 85 V V V V o C 0 Z R8A66162SP ELECTRICAL CHARACTERISTICS ■5.0V version support specifications (Ta=-40~85 C, Vcc=4.5V~5.5V, unless otherwise noted) o Symbol VT+ VTVOH Parameter Positive going threshold voltage Negative going threshold voltage High level SQ32 output voltage Low level Q1~Q32 output voltage Test conditions Min. 0.35xVcc Limits Typ. 0.20xVcc V 0.55xVcc V IIH High level input current VI=Vcc IOH=-20uA IOH=-4mA IOL=20uA IOL=24mA IOL=28mA IOL=20uA IOL=4mA Vcc=5.5V IIL IO Low level input current Maximum Q1~Q32 output leakage current Quiescent supply current VI=GND VI=VT+, VTVcc=5.5V Vcc=5.5V VO=Vcc VO=GND -5 10 -10 uA uA VI=Vcc, GND Vcc=5.5V 400 uA VOL VI=VT+, VTVcc=4.5V VI=VT+, VTVcc=4.5V Unit Max. 0.70xVcc SQ32 Icc Vcc-0.1 3.66 V 0.10 0.50 0.55(Note2) 0.10 0.53 5 V uA Note2 : Ta = -40~70oC ■3.3V version support specifications (Ta=-40~85 C, Vcc=3.0V~3.6V, unless otherwise noted) o Symbol VT+ VTVOH Parameter Positive going threshold voltage Negative going threshold voltage High level SQ32 output voltage Low level Q1~Q32 output voltage SQ32 Test conditions Min. 0.35xVcc 0.20xVcc Unit Max. 0.70xVcc V 0.55xVcc V IIH High level input current VI=Vcc IOH=-20uA IOH=-2mA IOL=20uA IOL=12mA IOL=20uA IOL=2mA Vcc=3.6V IIL IO Low level input current Maximum Q1~Q32 output leakage current Quiescent supply current VI=GND VI=VT+, VTVcc=3.6V Vcc=3.6V VO=Vcc VO=GND -5 10 -10 uA uA VI=Vcc, GND Vcc=3.6V 400 uA VOL Icc VI=VT+, VTVcc=3.0V VI=VT+, VTVcc=3.0V Limits Typ. REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 4 of 7 Vcc-0.1 2.60 V 0.10 0.54 0.10 0.40 5 V uA R8A66162SP o SWITCHING CHARACTERISTICS (Ta=-40~85 C, Vcc=5.0V or 3.3V, unless otherwise noted) Symbol fmax tPZL Parameter Test conditions Maximum clock frequency CK-Q1~Q32 Output “Z-L” and “L-Z” (Turned on) propagation time CK-Q1~Q32 (Turned off) Output “L-H” and “H-L” CK-SQ32 propagation time Output “Z-L” SD-Q1~Q32 propagation time (Turned on) Output “L-H” SD-SQ32 propagation time LE-Q1~Q32 Output “Z-L” and “L-Z” (Turned on) propagation time LE-Q1~Q32 (Turned off) Output “Z-L” and “L-Z” OE-Q1~Q32 propagation time (Turned on) OE-Q1~Q32 (Turned off) Input capacitance Output capacitance tPLZ tPLH tPHL tPZL tPLH tPZL tPLZ tPZL tPLZ CI CO Unit 5.0V specification Min. Typ. Max. 4 200 3.3V specification Min. Typ. Max. 3.3 220 250 270 ns CL=50pF 125 125 200 150 150 220 ns ns ns RL=1kΩ 125 150 ns (Note3) 125 150 ns 200 220 ns 125 150 ns 200 220 ns 10 15 10 15 pF pF OE=Vcc MHz ns o TIMING REQUIREMENTS (Ta=-40~85 C, Vcc=5.0V or 3.3V, unless otherwise noted) Symbol tw tsu th trec Parameter Test conditions CK, LE, SD pulse width Setup time A to CK Hold time A to CK Hold time LE to CK Recovery time CK to SD (Note3) 5.0V specification Min. Typ. Max. 125 125 15 70 70 Note3. Test circuit INPUT 3.3V specification Min. Typ. Max. 150 150 20 80 80 VCC VCC RL Q1∼Q32 DUT PG 50Ω SQ32 GND CL CL (1) The pulse generator(PG) has the following characteristics(10%~90%):tr=6ns,tf =6ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance. REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 5 of 7 Unit ns ns ns ns ns R8A66162SP TIMING DIAGRAM tw tw tw VCC VCC CK 50% 50% LE 50% 50% 50% GND GND SQ32 tPLH tPHL 50% 50% tPLZ tPZL 10% 50% tPZL VOL Q1 ∼ Q32 ∼ ∼VCC VOH Q1 ∼ Q32 50% VOL tPLZ ∼ ∼VCC VOL ∼ ∼VCC Q1 ∼ Q32 10% VOL tw VCC VCC 50% SD 50% A trec 50% 50% GND GND th tsu VCC CK 50% VCC CK 50% GND tPLH GND VOH 50% SQ32 VOL tPZL ∼ ∼VCC 50% Q1 ∼ Q32 VOL th VCC OE 50% 50% 50% GND tPLZ ∼ ∼VCC 10% VCC 50% GND tPZL Q1 ∼ Q32 LE CK VCC 50% GND VOL ∼ ∼VCC Q1 ∼ Q32 REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 6 of 7 VOL R8A66162SP PACKAGE OUTLINE Package 48pin SSOP RENESAS Code PRSP0048ZB-A Previous Code 48P2X-A All trademarks and registered trademarks are the property of their respective owners. REJ03F0263-0100 Rev.1.00 Jan.24.2008 page 7 of 7