MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM DESCRIPTION PIN DESCRIPTION This is a family of 4194304-word by 4-bit dynamic RAMS, Pin name Function fabricated with the high performance CMOS process, and is ideal A0 ~ A11 Address inputs for large-capacity memory systems where high speed, low power DQ1 ~ DQ4 Data inputs / outputs dissipation, and low costs are essential. RAS Row address strobe input CAS Column address strobe input W Write control input CMOS technology and a single-transistor dynamic storage stacked OE Output enable input capacitor cell provide high circuit density at reduced costs. VCC Power supply (+5V) Multiplexed address inputs permit both a reduction in pins and an VSS Ground (0V) The use of double-layer metal process combined with twin-well increase in system densities. PIN CONFIGURATION (TOP VIEW) FEATURES RAS CAS Address OE access access access access Cycle dissipa- time (max.ns) time (max.ns) time (max.ns) time (max.ns) time (min.ns) tion (typ.mW) M5M417400CXX-5,-5S 50 13 25 13 90 655 M5M417400CXX-6,-6S 60 15 30 15 110 540 M5M417400CXX-7,-7S 70 20 35 20 130 475 Type Name Power XX=J, TP • Standard 26 pin SOJ, 26 pin TSOP • Single 5V ± 10% supply • Low stand-by power dissipation 5.5mW(Max) ..................................CMOS Input level 2.2mW (Max)* ...............................CMOS Input level • Low operating power dissipation M5M417400Cxx-5,-5S .................... 800.0mW (Max) M5M417400Cxx-6,-6S .................... 660.0mW (Max) M5M417400Cxx-7,-7S .................... 580.0mW (Max) • Self refresh capability * self refresh current ................................ 200.0 µ A(Max) Outline 26P0D-B (300mil SOJ) • Fast-page mode, Read-modify-write, RAS-only refresh • CAS before RAS refresh, Hidden refresh capabilities Early-write mode and OE to control output buffer impedance • All inputs, output TTL compatible and low capacitance • 2048 refresh cycles every 32ms (A0 ~ A10) *Applicable to self refresh version (M5M417400CJ,TP-5S,-6S, -7S :option) only APPLICATION Main memory unit for computers, Microcomputer memory, Refresh memory for CRT Outline 26P3D-E (300mil TSOP) NC: NO CONNECTION 1 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM FUNCTION The M5M417400CJ,TP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Inputs Operation RAS CAS W Input/Output OE Row address Column address Input Output Refresh Read ACT ACT NAC ACT APD APD OPN VLD YES Write (Early write) ACT ACT ACT DNC APD APD VLD OPN YES Write (Delayed write) ACT ACT ACT DNC APD APD VLD IVD YES Read-modify-write ACT ACT ACT ACT APD APD VLD VLD YES RAS-only refresh ACT NAC DNC DNC APD DNC DNC OPN YES Hidden refresh ACT ACT NAC ACT APD DNC OPN VLD YES Self refresh ACT ACT NAC DNC DNC DNC DNC OPN YES CAS before RAS refresh ACT ACT NAC DNC DNC DNC DNC OPN YES Stand-by NAC DNC DNC DNC DNC DNC DNC OPN NO Remark Fast page mode identical Note: ACT: active, NAC: nonactive, DNC: don’t care, VLD: valid, IVD: invalid, APD: applied, OPN: open BLOCK DIAGRAM 2 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit -1 ~ 7 V -1 ~ 7 V VCC Supply voltage VI Input voltage VO Output voltage -1 ~ 7 V IO Output current 50 mA Pd Power dissipation 1000 mW Topr Operating temperature Tstg Storage temperature With respect to VSS Ta = 25°C 0 ~ 70 °C -65 ~ 150 °C RECOMMENDED OPERATING CONDITIONS (Ta = 0 ~ 70°C, unless otherwise noted) (Note 1) Symbol Limits Parameter Min Nom Max Unit VCC Supply voltage 4.5 5 5.5 V VSS Supply voltage 0 0 0 V VIH High-level input voltage, all inputs 2.4 5.5 V VIL Low-level input voltage, all inputs -1.0** 0.8 V Note 1: All voltage values are with respect to VSS. **: VIL(min.) is -2.0V when undershoot width is less than 25ns. (Undershoot width is with respect to VSS.) ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted) (Note 2) Symbol Parameter Test conditions Limits Min Max Unit VOH High-level output voltage IOH = -5.0mA 2.4 VCC VOL Low-level output voltage IOL = 4.2mA 0 0.4 V lOZ Off-state output current Q floating 0V ≤ VOUT ≤ 5.5V -10 10 µA II Input current 0V ≤ VIN ≤5.5V, Other inputs pins = 0V -10 10 µA Average supply current ICC1(AV) from VCC, operating (Note 3,4) M5M417400C-5,-5S RAS, CAS cycling 145 M5M417400C-6,-6S tRC = tWC = min. 120 M5M417400C-7,-7S output open 105 RAS = CAS = VIH, output open ICC2 Supply current from VCC, stand-by ICC3 (AV) ICC4 (AV) Note 2: 3: 4: 0.5 M5M417400C-5,-5S RAS cycling, CAS = VIH 145 M5M417400C-6,-6S tRC = min. 120 M5M417400C-7,-7S output open 105 Average supply current M5M417400C-5,-5S RAS = VIL, CAS cycling 80 from VCC, Fast-Page-Mode M5M417400C-6,-6S tPC = min. 70 M5M417400C-7,-7S output open 60 Average supply current from VCC, M5M417400C-5,-5S CAS before RAS refresh cycling 145 CAS before RAS refresh mode M5M417400C-6,-6S tRC = min. 120 M5M417400C-7,-7S output open 105 (Note 3) Current flowing into an IC is positive, out is negative. ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. V mA 2 RAS = CAS ≥ VCC -0.2V from VCC, refreshing (Note 3,4) ICC6 (AV) (Note 5) Average supply current (Note 3) 3 Typ mA mA mA mA MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM CAPACITANCE (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted) Symbol Parameter Limits Test conditions Min Typ Max Unit CI(A) Input capacitance, address inputs 5 pF CI(OE) Input capacitance, OE input 7 pF CI(W) Input capacitance, write control input VI = VSS 7 pF CI(RAS) Input capacitance, RAS input f = 1MHz VI = 25mVrms 7 pF CI(CAS) Input capacitance, CAS input 7 pF CI/O Input/Output capacitance, data ports 8 pF SWITCHING CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted, see notes 5, 12, 13) Limits Symbol Parameter M5M417400C-5,-5S Min Max M5M417400C-6,-6S Min Max M5M417400C-7,-7S Min Unit Max tCAC Access time from CAS (Note 6, 7) 13 15 20 tRAC Access time from RAS (Note 6, 8) 50 60 70 ns tAA Column address access time (Note 6, 9) 25 30 35 ns tCPA Access time from CAS precharge tOEA Access time from OE tCLZ Output low impedance time from CAS low (Note 6) 5 tOFF Output disable time after CAS high (Note 11) 0 13 0 15 Output disable time after OE high (Note 11) 0 13 0 15 tOEZ Note 5: ns (Note 6, 10) 30 35 40 ns (Note 6) 13 15 20 ns 0 15 ns 0 15 ns 5 5 ns An initial pause of 500 µ s is required after power-up followed by a minimum of eight initialization RAS cycles. The initialization cycles should be done either by RAS-only refresh cycles or by CAS before RAS refresh cycles only. Note the RAS may be cycled during the initial pause. And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 32ms) of RAS inactivity before proper device operation is achieved. After the initialization cycles, RAS should be kept either higher than VIH(min) or lower than VIL(max) except RAS transition time. 6: 7: Measured with a load circuit equivalent to 2 TTL loads and 100pF. Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max). 8: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 9: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max). 10: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 11: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ | ± 10 µA |) and is not reference to VOH(min) or VOL(max). 4 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles) (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted. See notes 12, 13) Limits Symbol Parameter M5M417400C-5,-5S Min Max M5M417400C-6,-6S Min 32 M5M417400C-7,-7S Max Min tREF Refresh cycle time tRP RAS high pulse width tRCD Delay time, RAS low to CAS low tCRP Delay time, CAS high to RAS low 10 10 10 ns tRPC Delay time, RAS high to CAS low 0 0 0 ns tCPN CAS high pulse width 10 10 10 tRAD Column address delay time from RAS low tASR Row address setup time before RAS low tASC Column address setup time before CAS low tRAH Row address hold time after RAS low tCAH Column address hold time after CAS low tDZC Delay time, data to CAS low (Note 17) tDZO Delay time, data to OE low tCDD 30 (Note 14) 18 (Note 15) 13 32 Unit Max 40 37 25 20 0 45 15 0 (Note 16) 20 30 15 0 10 32 ms 50 ns 50 ns ns 35 0 0 10 0 ns ns 10 ns 8 10 10 ns 13 15 15 ns 0 0 0 ns (Note 17) 0 0 0 ns Delay time, CAS high to data (Note 18) 13 15 15 ns tODD Delay time, OE high to data (Note 18) 13 tT Transition time (Note 19) 1 15 50 15 1 50 1 ns 50 ns Note 12: The timing requirements are assumed tT = 5ns. 13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) = tRAH(min) + 2tH + tASC(min). 15: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. 16: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. 17: Either tDZC or tDZO must be satisfied. 18: Either tCDD or tODD must be satisfied. 19: tT is measured between VIH(min) and VIL(max). Read and Refresh Cycles Limits Symbol Parameter M5M417400C-6,-6S M5M417400C-7,-7S Min Min Min Max Max 110 Unit Max tRC Read cycle time 90 tRAS RAS low pulse width 50 10000 60 10000 70 10000 tCAS CAS low pulse width 13 10000 15 10000 20 10000 tCSH CAS hold time after RAS low 50 60 70 ns tRSH RAS hold time after CAS low 13 15 20 ns tRCS Read setup time after CAS high 0 0 0 ns tRCH Read hold time after CAS low (Note 20) 0 0 0 ns tRRH Read hold time after RAS low (Note 20) 10 10 10 ns tRAL Column address to RAS hold time 25 30 35 ns tOCH CAS hold time after OE low 13 15 20 ns tORH RAS hold time after OE low 13 15 20 ns Note 20: Either tRCH or tRRH must be satisfied for a read cycle. 5 M5M417400C-5,-5S 130 ns ns ns MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Early Write and Delayed Write) Limits Symbol Parameter M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S Min Min Min Max Max tWC Write cycle time 90 tRAS RAS low pulse width 50 10000 60 10000 70 10000 tCAS CAS low pulse width 13 10000 15 10000 20 10000 tCSH CAS hold time after RAS low 50 60 70 tRSH RAS hold time after CAS low 13 15 20 ns tWCS Write setup time before CAS low 0 0 0 ns (Note 22) 110 Unit Max 130 ns ns ns ns tWCH Write hold time after CAS low 8 10 10 ns tCWL CAS hold time after W low 13 15 20 ns tRWL RAS hold time after W low 13 15 20 ns tWP Write pulse width 8 10 10 ns tDS Data setup time before CAS low or W low 0 0 0 ns tDH Data hold time after CAS low or W low tOEH OE hold time after W low 8 10 15 ns 13 15 20 ns Read-Write and Read-Modify-Write Cycles Limits Symbol Parameter (Note 21) M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S Min Min Min Max 131 Max 155 Unit Max tRWC Read write/read modify write cycle time tRAS RAS low pulse width 91 10000 105 10000 180 120 10000 ns tCAS CAS low pulse width 54 10000 60 10000 70 10000 tCSH CAS hold time after RAS low 91 105 120 tRSH RAS hold time after CAS low 54 60 70 ns tRCS Read setup time before CAS low 0 0 0 ns tCWD Delay time, CAS low to W low (Note 22) 36 40 45 ns tRWD Delay time, RAS low to W low (Note 22) 73 85 95 ns tAWD Delay time, address to W low (Note 22) 48 55 60 ns tCWL CAS hold time after W low 13 15 20 ns tRWL RAS hold time after W low 13 15 20 ns tWP Write pulse width 8 10 10 ns tDS Data setup time before W low 0 0 0 ns tDH Data hold time after W low tOEH OE hold time after W low ns ns ns 8 10 15 ns 13 15 15 ns Note 21: tRWC is specified as tRWC(min) = tRAC(max) + tODD(min) + tRWL(min) + tRP(min) + 5tT. Note 22: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate. 6 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) (Note 23) Limits Symbol Parameter M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S Min Min Min Max Max Unit Max tPC Fast page mode read/write cycle time 35 40 45 ns tPRWC Fast page mode read write/read modify write cycle time 76 85 95 ns tRAS RAS low pulse width for read write cycle (Note 24) 85 125000 100 125000 115 125000 ns tCP CAS high pulse width (Note 25) 8 12 10 15 10 15 ns tCPRH RAS hold time after CAS precharge 30 35 40 ns tCPWD Delay time, CAS precharge to W low (Note 22) 53 60 65 ns Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 24: tRAS(min) is specified as two cycles of CAS input are performed. 25: tCP(max) is specified as a reference point only. CAS before RAS Refresh Cycle (Note 26) Limits Symbol Parameter M5M417400C-5,-5S M5M417400C-6,-6S M5M417400C-7,-7S Min Min Min Max Max Unit Max tCSR CAS setup time before RAS low 10 10 10 ns tCHR CAS hold time after RAS low 10 10 15 ns tRSR Read setup time before RAS low 10 10 10 ns tRHR Read hold time after RAS low 10 10 15 ns Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. SELF REFRESH SPECIFICATIONS Self refresh devices are denoted by “S” after speed item, like -5S/-6S/-7S. The other characteristics and requirements than the below are same as normal devices. ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted) (Note 2) Symbol ICC8(AV) Parameter Average supply current from VCC Slow-Refresh cycle Test conditions Limits Min Typ Max CAS before RAS refresh cycling or RAS cycling & CAS ≤ 0.2V OE & WE ≤ 0.2V or OE & WE ≥ VCC - 0.2V M5M417400C (S) A0 ~ A10 ≤ 0.2V Unit 500 µA 200 µA or A0 ~ A10 ≥ VCC - 0.2V (Note 5) tREF = 128ms (2048 cycles) output = OPEN tRAS = tRASmin. ~ 1µs ICC9(AV) Average supply current from VCC Slow-Refresh cycle (Note 5) 7 M5M417400C (S) RAS = CAS ≤ 0.2V output = OPEN MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM TIMING REQUIREMENTS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted, see notes 12, 13) Limits Symbol Parameter M5M417400C-5S Min Max M5M417400C-6S Min Max M5M417400C-7S Min Unit Max tRASS Self Refresh RAS low pulse width 100 100 100 µs tRPS Self Refresh RAS high precharge time 90 110 130 ns tCHS Self Refresh RAS hold time -50 -50 -50 ns tRSR Read setup time before RAS low 10 10 10 ns tRHR Read hold time after RAS low 10 10 15 ns SELF REFRESH ENTRY & EXIT CONDITIONS 1. In case of distributed refresh The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh, on the condition of tNS ≤ 32ms and tSN ≤ 32ms. 2. In case of burst refresh The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh, on the condition of tNS + tSN ≤ 32ms. 8 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM TEST Mode SET Cycle Limits Symbol Parameter M5M417400C-5,-5S Min Max M5M417400C-6,-6S Min Max M5M417400C-7,-7S Min Unit Max tWSR W setup time before RAS low 10 10 10 ns tWHR W hold time after RAS low 10 10 15 ns Note 27: The test mode function is initiated by a W and CAS before RAS cycle (WCBR cycle) as specified in timing diagram. The test mode function is terminated by either a CAS before RAS refresh cycle (CBR refresh cycle) or a RAS only refresh cycle. During the test mode, the device is internally organized as 16-bits wide (1M bytes depth). No addressing of CA0 and CA1 is required. During a write cycle, data must be applied to all DQ (input) pins. The data can be different between DQ pins. The data on each DQ pin is written into 4-bits memory cells, respectively. During a read cycle, each DQ (output) pin shows the test result of the 4-bits, respectively. High state indicates that they are same. Low state indicates that they are not same. During the test mode operation, only WCBR cycle can be used to perform refresh. 9 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Timing Diagrams Read Cycle (Note 28) 10 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Early Write) 11 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Delayed Write) 12 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle 13 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM RAS-only Refresh Cycle 14 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM CAS before RAS Refresh Cycle, Slow Refresh Cycle 15 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 29) Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. And in any cycle, tRSR & tRHR should be satisfied not to enter TEST MODE. 16 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast Page Mode Read Cycle 17 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast Page Mode Write Cycle (Early Write) 18 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast-Page Mode Write Cycle (Delayed Write) 19 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Fast Page Mode Read-Write, Read-Modify-Write Cycle 20 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM Self Refresh Cycle 21 MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM TEST Mode SET Cycle Note 30: This cycle can be used for initialized cycle after power-up, however entried into Test Mode. 22