MITSUBISHI LSIs 1998.11.30 Ver.B M5M54R04AJ-10,-12,-15 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M5M54R04AJ is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS A0 1 A1 2 application. A2 3 address inputs A3 4 These devices operate on a single 3.3V supply, and are A 4 5 select directly TTL compatible. They include a power down chip input S 6 data inputs/ DQ 1 7 feature as well. outputs(3.3V) VCC 8 (0V) GND 9 FEATURES data inputs/ •Fast access time M5M54R04AJ-10 ... 10ns(max) DQ2 10 outputs M5M54R04AJ-12 ... 12ns(max) write control W 11 input M5M54R04AJ-15 ... 15ns(max) A5 12 A6 13 •Single +3.3V power supply address A7 14 inputs •Fully static operation : No clocks, No refresh A8 15 •Common data I/O A9 16 •Easy memory expansion by S •Three-state outputs : OR-tie capability Outline •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs silicon gate process and designed for high speed APPLICATION High-speed memory units 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 address inputs A16 A15 output enable OE input DQ4 data inputs/ GND (0V) outputs VCC (3.3V) DQ3 data inputs/ outputs A14 A13 address A12 inputs A11 A10 NC 32P0K(SOJ) PACKAGE M5M54R04AJ : 32pin 400mil SOJ BLOCK DIAGRAM adress inputs A0 1 A1 A2 2 A3 4 7 3 A4 5 A5 12 A6 13 MEMORY ARRAY 1024 ROWS 4096 COLUMNS DQ1 10 DQ2 23 DQ3 26 DQ4 data inputs/ outputs A7 14 A8 15 A9 16 S 6 COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS W 11 8 24 COLUMN INPUT BUFFERS OE 27 9 25 VCC (3.3V) GND (0V) 18 19 20 21 22 28 29 30 31 32 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 address inputs MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M54R04AJ is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a nonselectable mode in which both reading and writing are disable. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. FUNCTION TABLE S H W X OE X L L X L H L L H H Mode Non selection DQ High-impedance Icc Stand by Write Din Active Read Dout Active High-impedance Active ABSOLUTE MAXIMUM RATINGS Symbol Parameter V cc Supply voltage VI Input voltage VO Output voltage Pd Power dissipation T opr Operating temperature Conditions With respect to GND Ta=25°C Ratings Unit - 2.0 *~ 4.6 - 2.0*~ VCC+0.5 V - 2.0*~ VCC V V 1000 mW 0 ~ 70 °C Tstg(bias) Storage temperature(bias) - 10 ~ 85 °C T stg - 65 ~ 150 °C * Pulse Storage temperature width≤3ns, In case of DC: - 0.5V DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V Symbol VIH VIL VOH VOL II Parameter +10% - 5% ,unless otherwise noted) Limits Condition Min High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current 2.0 I OZ I OH = - 4mA IOL = 8mA VI= 0 ~ Vcc VI(S)=VIH Output current in off-state VI/O= 0 ~ Vcc I CC1 Active supply current (TTL level) VI(S)=VIL other inpus=VIH or VIL Output-open(duty 100%) I CC2 Stand by current (TTL level) VI(S)=VIH I CC3 Stand by current VI(S)=Vcc≥0.2V other inputs VI≤0.2V or VI ≥Vcc - 0.2V Typ Max 0.4 2 V V V V uA 2 uA Vcc+0.3 0.8 2.4 10ns cycle AC 12ns cycle 15ns cycle DC 10ns cycle AC 12ns cycle 15ns cycle DC Unit 190 180 160 90 90 70 60 40 10 mA mA mA Note 1: Direction for current flowing into an IC is positive (no mark). MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM CAPACITANCE (Ta=0~70°C, Vcc=3.3V Symbol Parameter +10% -5% ,unless otherwise noted) Test Condition Min Limit Typ Max Unit CI Input capacitance V I =GND, V I =25mVrms,f=1MHz 7 pF CO Output capacitance V O=GND, V O=25mVrms,f=1MHz 8 pF Note 2: CI,CO are periodically sampled and are not 100% tested. AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V +10% -5% ,unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels .................................... VIH=3.0V, VIL=0.0V Input rise and fall time .................................................... 3ns Input timing reference levels ........................ VIH=1.5V, VIL=1.5V Output timing reference levels ................. VOH =1.5V, VOL=1.5V Output loads ........................................................ Fig.1,Fig.2 5.0V OUTPUT Z0=50Ω 480Ω DQ DQ 255Ω RL=50Ω 5pF (including scope and JIG) VL=1.5V Fig.1 Output load Fig.2 Output load for ten , t dis MITSUBISHI ELECTRIC 3 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM (2)READ CYCLE Limits Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tv(A) tPU tPD Parameter Read cycle time M5M54R04AJ-10 Min 10 Address access time Chip select access time Output enable access time Output disable time after S high Output disable time after OE high Output enable time after S low Output enable time after OE low Data valid time after address change Power-up time after chip selection 0 0 2 0 2 0 Max 10 10 5 5 5 M5M54R04AJ-12 Max Min 12 12 12 6 6 6 0 0 3 1 3 0 10 Power-down time after chip selection M5M54R04AJ-15 Min 15 0 0 3 1 3 0 12 Unit Max 15 15 7 7 7 15 ns ns ns ns ns ns ns ns ns ns ns (3)WRITE CYCLE Limits Symbol Parameter M5M54R04AJ-10 Min tCW tw(W) tw(W) tsu(A)1 tsu(A)2 tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) tsu(A-WH) Write cycle time Write pulse width (OE low) Write pulse width(OE high) Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Address to W High Max 10 10 8 0 0 Min 12 Max 12 10 0 0 8 5 0 1 0 0 0 0 8 M5M54R04AJ-12 5 5 MITSUBISHI ELECTRIC M5M54R04AJ-15 Min 15 10 6 15 10 0 0 10 7 0 1 0 0 0 0 0 1 0 0 0 0 10 6 6 10 Unit Max 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~19 t CR VIH VIL ta(A) tv(A) DQ1~4 VOH tv(A) PREVIOUS DATA VALID VOL UNKNOWN DATA VALID W=H S=L OE=L Read cycle 2 (Note 3) t CR VIH S VIL ta(S) VOH UNKNOWN DATA VALID VOL tPU ICC1 Icc (Note 4) (Note 4) ten(S) DQ1~4 tdis(S) tPD 50% ICC2 50% W=H OE=L Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 5) t CR VIH OE VIL ta(OE) (Note 4) DQ1~4 VOH tdis(OE) (Note 4) ten(OE) UNKNOWN DATA VALID VOL W=H S=L Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM Write cycle (W control mode) t CW A 0~19 VIH VIL S VIH VIL tsu(S) (Note 6) (Note 6) tsu(A-WH) OE VIH VIL tsu(A) W tw(W) trec(W) VIH VIL tsu(D) DQ1~4 (Input Data) VIH VIL th(D) DATA STABLE tdis(W) (Note 4) ten(OE) ten(W) tdis(OE) DQ1~4 (Output Data) VOH VOL (Note 4) Hi-Z Write cycle(S control) t CW A 0~19 VIH VIL S VIH VIL tsu(A) tsu(S) trec(W) tw(W) W VIH VIL (Note 6) (Note 6) tsu(D) DQ1~4 (Input Data) VIH VIL DATA STABLE ten(S) DQ1~4 (Output Data) VOH VOL th(D) (Note 4) tdis(W) (Note 4) Hi-Z (Note 7) Note 6: Hatching indicates the state is don't care. 7: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 8: ten,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6