'97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION FEATURE Access Power supply current time Active Stand-by (max) (max) (max) Type M5M5255DP, FP-45LL 45ns M5M5255DP, FP-55LL 55ns PIN CONFIGURATION (TOP VIEW) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 DQ3 GND 14 M5M5255DP,FP The M5M5255DP,FP is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /W A13 A8 A9 A11 S2 A10 /S1 DQ8 DQ7 DQ6 DQ5 DQ4 Outline 28P4 (DP) 28P2W-C (DFP) 20µA (Vcc=5.5V) M5M5255DP, FP-70LL 70ns 55mA (Vcc=5.5V) M5M5255DP, FP-45XL 45ns 5µA (Vcc=5.5V) M5M5255DP, FP-55XL 55ns 0.05µA M5M5255DP, FP-70XL 70ns (Vcc=3.0V, Typical) •Single +5V power supply •No clocks, no refresh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •Simple memory expantion by /S1, S2 •Common Data I/O •Battery backup capability •Low stand-by current··········0.05µA(typ.) PACKAGE M5M255DP M5M5255DFP : 28 pin 600 mil DIP : 28 pin 450 mil SOP APPLICATION Small capacity memory units MITSUBISHI ELECTRIC 1 '97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION A read cycle is executed by setting /W at a high level while /S1 and S2 are in an active state(/S1="L", S2="H"). When setting /S1 at a high level or S2 at a low level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. The operation mode of the M5M5255DP,FP is determined by a combination of the device control inputs /S1, S2 and /W. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S1 or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. FUNCTION TABLE /S1 S2 /W Mode DQ Icc H X X Non selection High-impedance Stand-by L L X Non selection High-impedance Stand-by L H L Write DIN Active L H H Read DOUT Active FUNCTION TABLE A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 A 10 21 A 11 23 A9 24 WRITE CONTROL INPUT /W CHIP SELECT INPUT1 /S1 20 CHIP SELECT S2 INPUT2 (512 ROWS X 512 COLUMNS) CLOCK GENERATOR 27 22 MITSUBISHI ELECTRIC OUTPUT BUFFER 22 11 DQ1 12 DQ2 13 DQ3 15 DQ4 16 DQ5 17 DQ6 18 DQ7 19 DQ8 28 VCC (5V) 14 GND (0V) DATA I/O DATA INPUT BUFFER A 12 X 8BIT SENSE ANPLIFIER 1 ROW DECODER A 14 32768 WORD COLUMN DECODER 26 ADDRESS INPUT BUFFER 25 A 13 ADDRESS INPUT BUFFER ADDRESS INPUT A8 2 '97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage Vcc VI VO Pd Topr Tstg Conditions Input voltage Output voltage Power dissipation Operating temperature Storage temperature Ratings -0.3*~7.0 -0.3*~Vcc+0.3 With respect to GND Unit V V V mW (Max 7.0) 0~Vcc 700 0~70 -65~150 Ta=25°C °C °C * -3.0V in case of AC ( Pulse width ≤ 30ns ) DC ELECTRICAL CHARACTERISTICS Symbol (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted) Parameter Limits Test conditions Min Typ Max Unit 2.2 Vcc +0.3 V -0.3 0.8 V VIH High-level input voltage VIL Low-level input voltage VOH1 High-level output voltage 1 IOH=-1mA 2.4 V VOH2 High-level output voltage 2 IOH=-0.1mA Vcc -0.5 V VOL II Low-level output voltage IOL=2mA 0.4 V Input current VI=0~Vcc ±1 uA IO Output current in off-state /S1=VIH or S2=VIL or /OE=VIH VI/O=0~Vcc ±1 uA Icc1 Active supply current Icc2 Icc3 Icc4 35 50 (AC, MOS level ) 45ns /S1≤0.2V, S2>Vcc-0.2V Other inputs<0.2V or >Vcc-0.2V 55ns Output-open(duty 100%) 70ns 30 25 45 40 /S1=VIL,S2=VIH other inputs=VIH or VIL Output-open(duty 100%) 45ns 35 55 Active supply current 55ns 70ns 30 25 50 45 (AC, TTL level ) Stand-by current Stand-by current S2≤0.2V or /S1≥Vcc-0.2V, S2≥Vcc-0.2V other inputs=0~Vcc /S1=VIH or S2=VIL, other inputs=0~Vcc -LL mA mA 20 uA -XL 5 3 mA * -3.0V in case of AC ( Pulse width ≤ 30ns ) CAPACITANCE Symbol CI CO (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted) Parameter Input capacitance Output capacitance Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz Min Limits Typ Max 6 8 Unit pF pF Note 0: Direction for current flowing into an IC is positive (no mark). 1: Typical value is one at Ta = 25°C. 2: CI, CO are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 3 '97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) MEASUREMENT CONDITIONS (Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted ) Input pulse level···················VIH=2.4V,VIL=0.6V Input rise and fall time··········5ns Reference level····················VOH=VOL=1.5V Output loads·························Fig.1,CL=30pF (-45LL,-45XL ) CL=50pF (-55LL,-55XL ) CL=100pF (-70LL,-70XL ) CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) Vcc 1.8kΩ DQ 990Ω CL (Including scope and JIG) Fig.1 Output load (2) READ CYCLE Symbol Parameter tCR ta(A) ta(S1) ta(S2) tdis(S1) tdis(S2) ten(S1) ten(S2) tV(A) Read cycle time Address access time Chip select 1 access time Chip select 2 access time Output disable time after /S1 high Output disable time after S2 low Output enable time after /S1 low Output enable time after S2 high Data valid time after address -45LL, XL Min Max 45 45 45 45 15 15 5 5 10 Limits -55LL, XL Min Max 55 55 55 55 20 20 5 5 10 -70LL, XL Mi Max 70 70 70 70 25 25 5 5 10 Unit ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE -45LL, XL Min Max tCW 45 Write cycle time tw(W) Write pulse width 35 tsu(A) Address setup time 0 tsu(A-WH) Address setup time with respect to /W 40 tsu(S1) Chip select 1 setup time 40 tsu(S2) Chip select 2 setup time 40 tsu(D) Data setup time 20 th(D) Data hold time 0 trec(W) Write recovery time 0 tdis(W) Output disable time from /W low 15 ten(W) Output enable time from /W high 5 Symbol Parameter MITSUBISHI ELECTRIC Limits -55LL, XL Min Max 55 40 0 50 50 50 25 0 0 20 5 -70LL, XL Min Max 70 50 0 65 65 65 30 0 0 25 5 Unit ns ns ns ns ns ns ns ns ns ns ns 4 '97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM (4) TIMING DIAGRAMS Read cycle tCR A0~14 ta(A) tv (A) ta (S1) /S1 (Note 3) S2 tdis (S1) (Note 3) tdis (S2) (Note 3) ta (S2) ten (S1) (Note 3) ten (S2) DATA VALID DQ1~8 /W = "H" level Write cycle (/W control mode) tCW A0~14 tsu (S1) /S1 (Note 3) (Note 3) S2 tsu (S2) (Note 3) (Note 3) tsu (A-WH) tsu (A) tw (W) trec (W) /W tdis (W) DQ1~8 ten (W) DATA IN STABLE tsu (D) MITSUBISHI ELECTRIC th (D) 5 '97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM Write cycle ( /S1 control mode) tCW A0~14 tsu (A) tsu (S1) trec (W) /S1 S2 (Note 3) (Note 3) (Note 5) /W (Note 4) (Note 3) tsu (D) th (D) (Note 3) DATA IN STABLE DQ1~8 Write cycle (S2 control mode) tCW A0~14 /S1 (Note 3) (Note 3) tsu (A) tsu (S2) trec (W) S2 (Note 5) /W (Note 4) (Note 3) DQ1~8 tsu (D) th (D) (Note 3) DATA IN STABLE Note 3 : Hatching indicates the state is "don't care". 4 : Writing is executed while S2 high overlaps /S1 and /W low. 5 : When the falling edge of /W is simultaneously or prior to the falling edge of /S1 or rising edge of S2, the outputs are maintained in the high impedance state. 6 : Don't apply inverted phase signal externally when DQ pin is output mode. MITSUBISHI ELECTRIC 6 '97.4.7 MITSUBISHI LSIs M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc (PD) (Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted) Parameter Test conditions Min 2 2.2 Power down supply voltage 2.2V≤VCC(PD) VI (/S1) Chip select input /S1 VI (S2) Chip select input S2 Icc (PD) Power down supply current 2V≤VCC(PD)≤2.2V Limits Typ Max V V VCC(PD) V 4.5V≤VCC(PD) VCC(PD)<4.5V Vcc = 3V S2≤0.2V or /S1≥Vcc-0.2V,S2≥Vcc-0.2V Unit 0.8 0.2 10 -LL (Note 7) -XL 0.1 2 uA (Note 8) Note7: ICC (PD) = 1uA in case of Ta = 25°C Note8: ICC (PD) = 0.5uA in case of Ta = 25°C (2) TIMING REQUIREMENTS (Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted ) Symbol tsu (PD) trec (PD) Parameter Test conditions Power down set up time Power down recovery time Min Limits Typ Max Unit ns ns 0 tCR (3) POWER DOWN CHARACTERISTICS /S1 control mode Vcc tsu (PD) 4.5V 4.5V trec (PD) 2.2V 2.2V /S1≥Vcc-0.2V /S1 S2 control mode Vcc tsu (PD) S2 4.5V 4.5V 0.2V trec (PD) 0.2V S2≤0.2V MITSUBISHI ELECTRIC 7