MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION Those are summarized in the part name table below. The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs organized as 262,144-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.25µm CMOS technology . The M5M5V416B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V416BUG is packaged in a CSP (chip scale package), with the outline of 7mm x 8.5mm, ball matrix of 6 x 8 (48pin) and ball pitch of 0.75mm. It giv es the best solution f or a compaction of mounting area as well as f lexibility of wiring pattern of printed circuit boards. I-v ersion -40 ~ +85°C Single +2.7~+3.6V power supply Small stand-by current: 0.3µA(3V,ty p.) No clocks, No ref resh Data retention supply v oltage =2.0V to 3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S1, S2, BC1 and BC2 Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus Process technology : 0.25µm CMOS Package: 48pin 7mm x 8.5mm CSP Activ e current ty pical * Ratings (max.) Icc1 25°C 40°C 25°C 40°C 70°C 85°C (3.0V, ty p.) Stand-by c urrent Icc (PD), Vcc=3.0V Version, Operating temperature FEATURES Power Supply Part name M5M5V416BUG -70HI Access time max. 70ns 2.7 ~ 3.6V 0.3µA 1µA 1µA 3µA 15µA 30µA 50mA (10MHz) 7mA (1MHz) * "ty pical" parameter is sampled, not 100% tested. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 A1 A2 S2 A4 S1 DQ1 A BC1 OE A0 B DQ9 BC2 A3 C DQ10 DQ11 A5 A6 DQ2 DQ3 D GND DQ12 A17 A7 DQ4 VCC Pin A0 ~ A17 E VCC DQ13 GND A16 DQ5 GND F DQ15 DQ14 A14 A15 DQ6 DQ7 G DQ16 N.C. A12 A13 W DQ8 H N.C. A8 A9 A10 A11 N.C. Function Address input DQ1 ~ DQ16 Data input / output S1 Chip select input 1 S2 Chip select input 2 W Write control input OE Output enable input BC1 Lower By te (DQ1 ~ 8) BC2 Upper By te (DQ9 ~ 16) Vcc Power supply GND Ground supply Outline: 48FJA NC: No Connection MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5V416BWG is organized as 262,144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy cle and must be stable during the entire cycle. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode. When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply c urrent is reduced as low as 0.3µA(25°C, ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE BLOCK DIAGRAM S1 S2 BC1 BC2 W OE H X X X X X Non selection DQ9~16 Icc High-Z High-Z Standby X L X X X X Non selection High-Z High-Z Standby X X L H L H H L L H H H X L H X X L Non selection High-Z High-Z Standby Din High-Z Activ e Dout High-Z Activ e L L L L L L L L H H H L L L H L L L L L L H L H H L H H H X L H X L H H H H H H H H A0 Mode Write Read Write Read Write Read DQ1~8 High-Z High-Z High-Z Din High-Z Dout High-Z High-Z Din Din Dout Dout High-Z High-Z Activ e Activ e Activ e Activ e Activ e Activ e Activ e DQ 1 A1 MEMORY ARRAY DQ 8 262144 WORDS x 16 BITS A 16 - DQ 9 A 17 S1 CLOCK GENERATOR DQ 16 S2 BC1 Vcc BC2 W GND OE MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vcc Supply v oltage With respect to GND -0.5 * ~ +4.6 VI Input v oltage With respect to GND -0.5 * ~ Vcc + 0.5 VO Output v oltage With respect to GND 0 ~ Vcc Pd Power dissipation Ta=25°C 700 Ta Operating temperature I-v ersion - 40 ~ +85 °C - 65 ~ +150 °C T stg Conditions Ratings Storage temperature Units V mW * -3.0V in case of AC (Pulse width < = 30ns) DC ELECTRICAL CHARACTERISTICS Symbol ( Vcc=2.7 ~ 3.6V, unless otherwise noted) Parameter Limits Conditions Min V IH V IL V OH1 V OH2 V OL II IO High-lev el input v oltage 2.2 -0.3 * 2.4 Output leakage current BC1 and BC2=VIH or S1=VIH or S2=VIH or OE=VIH, VI/O=0 ~ Vcc Icc 1 Activ e supply c urrent ( AC,MOS lev el ) BC1 and BC2< = 0.2V, S1< = 0.2V, S2 Vcc-0.2V > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) f = 10MHz BC1 and BC2=V IL , S=V IL ,S2=V IH other pins =V IH or V IL Output - open (duty 100%) f = 10MHz Icc 2 Activ e supply c urrent ( AC,TTL lev el ) Low-lev el input v oltage High-level output voltage 1 High-level output voltage 2 Low-lev el output v oltage Input leakage current I OH= -0.5mA I OH= -0.05mA I OL=2mA V I =0 ~ Vcc ( AC,MOS lev el ) 0.6 V 0.4 ±1 ±1 70 15 70 50 7 50 - 7 - 15 +85°C +70°C - - 20 +40°C - 1 5.0 0 ~ +25°C - 0.3 2.0 - 20 ~ +25°C - 0.3 2.0 - 40 ~ +25°C - 0.3 2.0 - - 0.5 f = 1MHz other inputs = 0 ~ Vcc <2> S2 Units Vcc+0.3V - f = 1MHz > S1 = Vcc - 0.2V, Stand by s upply current Max Vcc-0.5V <1> Icc 3 Ty p 0.2V, other inputs = 0 ~ Vcc µA mA 40 µA <3> BC1 and BC2 => Vcc - 0.2V > S1 < = 0.2V, S2 = Vcc - 0.2V Other inputs=0~Vcc Icc 4 Stand by s upply current ( AC,TTL lev el ) BC1 and BC2=VIH or S1=VIH or S2=VIL Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=3.0V and Ta=25° C CI CO Parameter * -3.0V in case of AC (Pulse width < = 30ns) (Vcc=2.7 ~ 3.6V, unless otherwise noted) CAPACITANCE Symbol mA Conditions Min Input capacitance V I =GND, VI =25mVrms, f =1MHz Output capacitance V O = GND,VO =25mVrms, f =1MHz MITSUBISHI ELECTRIC Limits Ty p Max 10 10 Units pF 3 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS (Vcc=2.7 ~ 3.6V, unless otherwise noted) 2.7V~3.6V V IH=2.4V,V IL=0.4V Input rise time and f all time 5ns Supply v oltage 1TTL Input pulse Ref erence lev el Output loads DQ CL V OH=V OL=1.5V Transition is measured ±500mV f rom steady state voltage.(f or ten,t dis ) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Fig.1 Output load (2) READ CYCLE Limits Units Symbol Parameter t CR t a(A) t a(S1) t a(S2) t a(BC1) t a(BC2) t a(OE) t dis (S1) t dis (S2) t dis (BC1) t dis (BC2) t dis (OE) t en(S1) t en(S2) t en(BC1) t en(BC2) t en(OE) Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1 high Output disable time af t er S2 low Output disable time af t er BC1 high Output disable time af t er BC2 high Output disable time af t er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low t V(A) Data v alid time after address Min Max 70 70 70 70 70 70 35 25 25 25 25 25 10 10 10 10 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Limits Symbol Units Parameter Min t CW Write cy cle time t w(W) Write pulse width t su(A) Address setup time t su(A-WH) Address setup time with respect to W t su(BC1) By te control 1 setup time t su(BC2) By te control 2 setup time t su(S1) Chip select 1 setup time t su(S2) Chip select 2 setup time t su(D) Data setup time t h(D) Data hold time t rec (W) Write recov ery time t dis (W) Output disable time f rom W low t dis (OE) Output disable time f rom OE high t en(W) Output enable time f rom W high t en(OE) Output enable time f rom OE low Max 70 55 0 60 60 60 60 60 35 0 0 25 25 5 5 MITSUBISHI ELECTRIC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~17 t a(BC1) t a(A) or t a (BC2) t v (A) BC1,BC2 (Note3) t dis (BC1) or t dis (BC1) (Note3) t a(S1) S1 (Note3) t dis (S1) (Note3) t dis (S2) (Note3) t a(S2) S2 (Note3) t a (OE) OE (Note3) t en (OE) W = "H" lev el DQ 1~16 Write cycle ( W control mode ) t dis (OE) t en (BC1) t en (BC2) t en (S1) t en (S2) (Note3) VALID DATA t CW A 0~17 t su (BC1) or t su (BC2) BC1,BC2 (Note3) (Note3) t su (S1) S1 (Note3) (Note3) t su (S2) S2 (Note3) (Note3) OE t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W t en (OE) t en (W) t dis (OE) DQ 1~16 DATA IN STABLE t su (D) t h (D) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC control mode) t CW A 0~17 t su (A) t su (BC1) or t su (BC2) t rec (W) BC1,BC2 S1 (Note3) (Note3) S2 (Note3) W (Note4) (Note3) DQ 1~16 (Note3) (Note5) t su (D) t h (D) (Note3) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1 or rising edge of S2, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S1 control mode) t CW A 0~17 BC1,BC2 (Note3) t su (S1) t su (A) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) t su (D) t h (D) (Note3) DATA IN STABLE DQ 1~16 Write cycle (S2 control mode) t CW A 0~17 BC1,BC2 (Note3) t su (A) t su (S2) t rec (W) (Note3) S1 S2 (Note3) (Note3) (Note5) W (Note4) (Note3) DQ 1~16 t su (D) t h (D) (Note3) DATA IN STABLE MITSUBISHI ELECTRIC 7 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc Limits Parameter Test conditions Min (PD) Power down supply voltage V I (BC) Chip select input S1 V I (S2) Chip select input S2 (PD) 3) S2 0.2V other inputs=0~3V t su (PD) t rec (PD) V V 0.2 V - 30 µA +70°C - - 15 µA +40°C - 1 3 µA 0 ~ +25°C - 0.3 1 µA -20 ~ +25°C - 0.3 1 µA -40 ~ +25°C - 0.3 1 µA Typical value is for Ta=25°C (2) TIMING REQUIREMENTS Symbol V - 1) BC1 and BC2 > = Vcc-0.2V S1 < =0.2V or S2 > = Vcc-0.2V other inputs=0~3V 2) S1 > =Vcc - 0.2V other inputs=0~3V Power down supply c urrent Units +85°C Vcc=3.0V Icc Max 2.0 2.0 2.0 Byte control input BC1 & BC2 V I (S1) Ty p Limits Parameter Test conditions Min Ty p Max 0 5 Power down set up time Power down recov ery t ime Units ns ms (3) TIMING DIAGRAM BC control mode Vcc t su (PD) BC1 2.7V 2.7V t rec (PD) 2.2V 2.2V BC1 , BC2 > = Vcc - 0.2V BC2 Note 7: On the S1 mode , the lev el of S2 must be f ixed at S2 > = Vcc - 0.2V or S2 S1 control mode Vcc t su (PD) 2.7V 2.7V 0.2V. t rec (PD) 2.2V 2.2V S1 > = Vcc - 0.2V S1 S2 control mode Vcc S2 t su (PD) 0.2V 2.7V 2.7V t rec (PD) S2 0.2V MITSUBISHI ELECTRIC 0.2V 8 MITSUBISHI LSIs revision-01, 17th July '00 M5M5V416BUG - 70H I 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Revision History Revision No. 01 History Date The first edition 17th July '00 MITSUBISHI ELECTRIC Remark 9 Keep safety first in your circuit designs! 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