2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM Those are summarized in the part name table below. FEATURES DESCRIPTION The M5M5W816TP is a f amily of low v oltage 8-Mbit static RAMs organized as 524288-words by 16-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5W816TP is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. The M5M5W816TP is packaged in a 44pin thin small outline mount dev ice, with the outline of 400mil TSOP TY PE(II). It giv es the best solution f or a compaction of mounting area as well as f lexibility of wiring pattern of printed circuit boards. The operating temperature range is -40~+85°C Version, Power Supply Operating temperature Part name I-version M5M5W816TP -70HI -40~+85°C M5M5W816TP -85HI Access time max. - Single 2.7~3.0V power supply Small stand-by current: 0.2µA (3.0V, ty p.) No clocks, No ref resh Data retention supply v oltage =2.0V All inputs and outputs are TTL compatible. Easy memory expansion by S#, BC1# and BC2# Common Data I/O Three-state outputs: OR-tie capability OE# prev ents data contention in the I/O bus Process technology : 0.18µm CMOS Package: 44pin 400mil TSOP TYPE(II) Stand-by c urrent Ratings (max.) * Ty pical 25°C 40°C 25°C 40°C 70°C 85°C 70ns 2.7~3.0V 0.5 1.0 2 85ns 4 20 40 Activ e current Icc1 *(ty p.) 40mA (10MHz) 5mA (1MHz) * Typical parameter indicates the value for the center of distribution, and not 100% tested. PIN CONFIGURATION A4 A3 A2 A1 A0 S# DQ1 DQ2 DQ3 DQ4 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 A5 A6 A7 OE# BC2# BC1# DQ16 DQ15 DQ14 DQ13 V CC 11 34 GND GND DQ5 DQ6 DQ7 DQ8 W# A15 A14 A13 A12 A16 12 33 V CC 13 32 DQ12 DQ11 DQ10 DQ9 A18 A8 A9 A10 A11 A17 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 Pin A0 ~ A18 Function Address input DQ1 ~ DQ16 Data input / output 44Pin 400mil TSOP S# W# OE# Chip select input BC1# Lower By te (DQ1 ~ 8) BC2# Upper By te (DQ9 ~ 16) Vcc Power supply GND Ground supply Write control input Output enable input Outline: 44P3W NC: No Connection MITSUBISHI ELECTRIC 1 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION The M5M5W816TP is organized as 524288-words by 16bit. These dev ices operate on a single +2.7~3.0V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1# , BC2# , S# , W# and OE#. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W# ov erlaps with the low lev el BC1# and/or BC2# and the low lev el S#. The address(A0~A18) must be set up bef ore the write cy c le and must be stable during the entire cy c le. A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while BC1# and/or BC2# and S# are in an activ e state(S#=L). When setting BC1# at the high lev el and other pins are in an activ e stage , upper-by t e are in a selectable mode in which both reading and writing are enabled, and lower-by t e are in a non-selectable mode. And when setting BC2# at a high lev el and other pins are in an activ e stage, lowerby t e are in a selectable mode and upper-by te are in a non-selectable mode. The operating temperature range is -40 ~ +85°C When setting BC1# and BC2# at a high lev el or S# at a high lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S#. The power supply c urrent is reduced as low as 0.1µA(25°C, ty pical), and the memory data can be held at +2.0V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE S# BC1# BC2# W# OE# H X L L L L L L L L L X H L L L H H H L L L X H H H H L L L L L L X X L H H L H H L H H X X X L H X L H X L H Mode Non selection Non selection Write Read Write Read Write Read DQ1~8 High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z DQ9~16 Icc High-Z Standby High-Z Standby High-Z Activ e High-Z Activ e High-Z Activ e Din Activ e Dout Activ e High-Z Activ e Din Activ e Dout Activ e High-Z Activ e BLOCK DIAGRAM A0 DQ 1 A1 MEMORY ARRAY DQ 8 524288 WORDS x 16 BITS A 17 - DQ 9 A 18 CLOCK GENERATOR S# DQ 16 BC1# Vcc BC2# W# GND OE# MITSUBISHI ELECTRIC 2 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vcc VI VO Pd Power dissipation Ta Operating temperature T stg Conditions Supply v oltage Input v oltage With respect to GND Output v oltage With respect to GND -0.3 * ~ +4.6 -0.3 * ~ Vcc + 0.3 (max. 4.6V) 0 ~ Vcc 700 With respect to GND Ta= Units Ratings 25°C Storage temperature V mW - 40 ~ +85 °C - 65 ~ +150 °C * -3.0V in case of AC (Pulse width < = 30ns) ( Vcc=2.7 ~ 3.0V, unless otherwise noted) DC ELECTRICAL CHARACTERISTICS Symbol V IH V IL V OH V OL II IO Parameter Limits Conditions Min High-lev el input v oltage Low-lev el input v oltage High-level output voltage Low-lev el output v oltage Input leakage current Output leakage current I OH= - 0.5mA I OL=2mA V I =0 ~ Vcc 0.6 f = 10MHz f = 1MHz - 5 10 ~ +25°C 0.5 2 ~ +40°C - 1.0 4 ~ +70°C - - 20 ~ +85°C - - 40 - - 2 BC1# and BC2#=V IL , S#=V IL other pins =V IH or V IL Output - open (duty 100%) (1) S# = > Vcc - 0.2V, other inputs = 0 ~ Vcc Stand by s upply current ( AC,TTL lev el ) -0.2 * 2.4 30 5 30 Activ e supply c urrent Icc 2 ( AC,TTL lev el ) Icc 4 Vcc+0.2V - f = 10MHz ( AC,MOS lev el ) 2.2 BC1# and BC2#=VIH or S#=VIH or OE#=VIH, VI/O=0 ~ Vcc < 0.2V, S# < 0.2V BC1# and BC2# = = > other inputs < = 0.2V or = Vcc-0.2V Output - open (duty 100%) Icc 3 Stand by s upply current (2) BC1# and BC2# = > Vcc - 0.2V S# <= 0.2V other inputs = 0 ~ Vcc f = 1MHz BC1# and BC2#=VIH or S#=VIH Other inputs= 0 ~ Vcc Note 1: Direction for current flowing into IC is indicated as positive (no mark) Max 0.4 ±1 ±1 40 10 40 Icc 1 Activ e supply c urrent ( AC,MOS lev el ) Ty p Units V µA mA µA mA * -3.0V in case of AC (Pulse width < = 30ns) Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested. CAPACITANCE Symbol CI CO Parameter (Vcc=2.7 ~3.0V, unless otherwise noted) Conditions Min Input capacitance V I =GND, VI =25mVrms, f =1MHz Output capacitance V O = GND,VO =25mVrms, f =1MHz MITSUBISHI ELECTRIC Limits Ty p Max 10 10 Units pF 3 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS (Vcc=2.7 ~3.0V, unless otherwise noted) 1TTL 2.7~3.0V Input pulse V IH=2.4V, V IL=0.4V Input rise time and f all time 5ns Supply v oltage Ref erence lev el V OH=V OL=1.5V DQ CL Transition is measured ±200mV from steady state voltage.(for ten,tdis) Including scope and jig capacitance Fig.1,CL=30pF CL=5pF (for ten,tdis) Output loads Fig.1 Output load (2) READ CYCLE Limits Parameter Symbol t CR t a(A) t a(S) t a(BC1) t a(BC2) t a(OE) t dis (S) t dis (BC1) t dis (BC2) t dis (OE) t en(S) t en(BC1,2) t en(OE) t V(A) 85HI 70HI Read cy cle time Address access time Chip select 1 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S# high Output disable time af t er BC1# high Output disable time af t er BC2# high Output disable time af t er OE# high Output enable time af ter S# low Output enable time af ter BC1#,BC2# low Output enable time af ter OE# low Data v alid time after address Min 70 Max Min 85 Units Max 70 70 70 70 35 25 25 25 25 85 85 85 85 45 30 30 30 30 10 5 5 10 10 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5ns in case of using either BC1# or BC2# (3) WRITE CYCLE Limits Symbol t CW t w(W) t su(A) t su(A-WH) t su(BC1) t su(BC2) t su(S) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) 70HI Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W# By te control 1 setup time By te control 2 setup time Chip select setup time Data setup time Data hold time Write recov ery time Output disable time f rom W# low Output disable time f rom OE# high Output enable time f rom W# high Output enable time f rom OE# low Min 70 55 0 65 65 65 65 35 0 0 85HI Max Min 85 60 0 70 70 70 70 45 0 0 30 30 25 25 5 5 5 5 MITSUBISHI ELECTRIC Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle t CR A 0~18 t v (A) t a(A) t a(BC1) or t a(BC2) BC1#,BC2# (Note3) t dis (BC1) or t dis (BC2) (Note3) t dis (S) (Note3) t dis (OE) (Note3) t a(S) S# (Note3) t a (OE) OE# (Note3) t en (OE) W# = "H" lev el t en (BC1) t en (BC2) t en (S) DQ 1~16 Write cycle ( W# control mode ) VALID DATA t CW A 0~18 t su (BC1) or t su (BC2) BC1#,BC2# (Note3) (Note3) t su (S) S# (Note3) (Note3) OE# t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W# t en (OE) t en (W) t dis (OE) DQ 1~16 DATA IN STABLE t su (D) t h (D) MITSUBISHI ELECTRIC 5 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (BC# control mode) t CW A 0~18 t su (A) t su (BC1) or t su (BC2) t rec (W) BC1#,BC2# S# (Note3) (Note3) (Note5) W# (Note4) (Note3) (Note3) t su (D) DQ 1~16 t h (D) DATA IN STABLE Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S# low ov erlaps BC1# and/or BC2# low and W# low. Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of S#, the outputs are maintained in the high impedance state. Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode. MITSUBISHI ELECTRIC 6 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM Write cycle (S# control mode) t CW A 0~18 BC1#, BC2# (Note3) t su (A) t su (S) t rec (W) (Note3) S# (Note5) W# (Note4) (Note3) DQ 1~16 t su (D) t h (D) (Note3) DATA IN STABLE MITSUBISHI ELECTRIC 7 2001.4.11 Ver. 2.0 MITSUBISHI LSIs M5M5W816TP-70HI, 85HI PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Vcc Parameter Min (PD) Power down supply voltage V I (BC) Byte control input BC1# & BC2# V I (S) Icc Test conditions (PD) Chip select input S# Power down supply c urrent Limits Ty p Max 2.0 V 2.0 V 2.0 V Vcc=2.0V ~ +25°C 1.5 ~ +40°C - 0.1 (1) S# => Vcc - 0.2V, 0.2 3 (2) BC1# and BC2#=> Vcc - 0.2V ~ +70°C - - 15 ~ +85°C - - 30 other inputs = 0 ~ Vcc S# < = 0.2V other inputs = 0 ~ Vcc Units µA Note 2: Typical parameter of Icc(PD) indicates the value for the center of distribution at 2.0V, and not 100% tested. (2) TIMING REQUIREMENTS Symbol t su (PD) t rec (PD) Limits Parameter Test conditions Min Ty p 0 5 Power down set up time Power down recov ery t ime Max Units ns ms (3) TIMING DIAGRAM BC# control mode Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V BC1# BC2# BC1# , BC2# > = Vcc-0.2V S# control mode Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V S# S# > = Vcc-0.2V MITSUBISHI ELECTRIC 8 Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 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