MITSUBISHI M61506FP

MITSUBISHI SOUND PROCESSORS
M61506FP
Peak hold IC for 5 band spectrum analyzer displays
DESCRIPTION
The M61506FP is a 5 band peak hold ICs that use microprocessor time division to produce
serial output for spectrum analyzer displays.
FEATURES
5 band peak hold elements for spectrum analyzer displays.
Discharge time constant circuit for each band is on the chip.
Single 5V power supply.
RECOMMENDED OPERATING CONDITIONS
Supply voltage range
4.5 to 6.5V
Rated supply voltage
5.0 V
SYSTEM BLOCK DIAGRAM
Audio
signal
BPF5 Peak
BPF5 Peak
Peak
BPF5 Hold5
Peak
BPF5 Hold5
Peak
BPF5 Hold5
Hold5
Hold5
Peak
SELECTOR
Hold
output
µ-com
interface
SELA
SELC
SELB
ENB
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BLOCK DIAGRAM
Vcc/2
1
Vcc/2 Gen.
VREF
2
V REF Gen.
16 GND2
SELECTOR
15 PHOUT
(VccX0.3)
IREF
TEST
I REF Gen.
3
HOLD
OUTPUT
BPF IN
DIFOUT
4
13 ENB
2K
+
D
P.HOLD
f2 BPF 2
P.HOLD
5
12 SELC
Amp-
f3 BPF 3
P.HOLD
f4 BPF 4
P.HOLD
+
C
CNF
f1 BPF 1
Amp-
2K
COUT
11 SELB
6
f5 BPF 5
AOUT
7
14 GND1
P.HOLD
<PEAK HOLD>
10 SELA
2K
Amp-A
+
ANF
HOLD C RESET
8
9
Vcc
(Notes)f1=105Hz,f2=340Hz,f3=1KHz,f4=3.4KHz,f5=10.5KHz
(The value is the design value)
Units Resistance :Ω
Capacitance: F
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FUNCTIONAL DESCRIPTION
(1)The audio signal amplified by Amp-A and Amp-D into BPF/peak
hold circuit for spectrum analyzer display.
Because the last output signal inputs into A/D of microprocessor.
The Vcc,GND had better be common with Vcc,GND of A/D of
maicroprocessor.
It untilizes effect of common-mode rejection of Amp-D.Amp-C is the input
amplifier to reject common-mode signal(noise).To get to good ground isolation.
(2)BPF/peak hold circuit is fit for 5 band spectrum analyzer display.
<center frequency>
f1=105Hz
f2=340Hz
f3=1KHz
f4=3.4KHz
f5=10.5KHz
(The value is the design value)
Center frequency and Q of BPF is
ω0=gm/C
gm:matual condactance of inside amplifier circuit
(It depends on outside resistor value of Pin.No.3)
C:inside capacitor
Q=(R1+R2)/R1:it is fixed by inside resistor ratio.
(The design value of Q is 3.5)
(3)The hold capacitor of peak hold circuit is included.
The reset(discharge) signal is made automatically after ending the output
of hold value(Discharge pulse effect:-3dB(typ).fall refer to output value)
(4)The internal output voltage of peak hold circuit is refered to Vcc/2.
(Pin.No.1)
When it is selected by the output select circuit,it appear at PHout
(Pin.No.15) refered to GND.
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PIN DESCRIPTION
PIN No.
Name
I/O
Function
1
Vcc/2
I
1/2Vcc bias
2
VREF
I
0.3Vcc bias
3
IREF
I
BPF center frequency setting current terminal
4
DIFOUT
O
Output of amplifier-D(BPF input signal)
5
COUT
O
Output of amplifier-C
6
CNF
I
Inverted input of amplifier-C
7
AOUT
O
Output of amplifier-A
8
ANF
I
Inverted input of amplifier-A
9
Vcc
I
System supply
10
SELA
I
Output setting control terminal A(logic input)
11
SELB
I
Output setting control terminal B(logic input)
12
SELC
I
Output setting control terminal C(logic input)
13
ENB
I
Output setting control enable terminal(logic input)
14
GND1
I
Ground 1
15
PHOUT
O
Peak hold output terminal
16
GND2
I
Ground 2
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PIN No.
1
2
Name
Vcc/2
VREF
I
Vcc
I
180K
1
180K
3
IREF
I
4
DIFOUT
O
5
COUT
O
6
CNF
I
7
AOUT
O
350K
2
3
150K
GND2
Vcc/2
6
5
2K
2K
Vcc/2
8
8
ANF
I
9
Vcc
I
SELA
I
10
Peripheral circuit of pins
I/O
2K
4
7
Supply
10,11,12,13
11
SELB
I
VccX0.3
20K
12
SELC
I
10K
VccX0.3
13
ENB
I
14
GND1
I
15
PHOUT
O
16
GND2
I
Ground1
10K
GND2
15
Ground2
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ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Vcc(max)
Conditions
Supply Voltage
Ratings
Unit
7
V
Pd
Power dissipation
Ta<25
=
C
540
mW
K
Thermal derating
Ta>25
C
5.4
mW/ C
Topr
Operating temperature
-20 to +75
C
Tstg
Storage temperature
-40 to +125
C
Vi(max)
Input voltage range
Vo(max)
Output voltage range
GND-0.3 to Vcc+0.3
V
GND to Vcc
V
Thermal derating(maximum rating)
0.6
0.54
0.5
0.4
0.3
0.27
0.2
0.1
0
0
25
50
75
100
AMBIENT TEMPERATURE Ta (
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150
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Recommended operating conditions
(Ta=25 C unless otherwise noted)
Parameter
Supply voltage
Logic input H
level voltage
Logic input L
level voltage
Symbol
Conditions
Vcc
MIN
TYP
MAX
4.5
5.0
6.5
V
VCC
V
0.5
V
VIH
Vcc=5V
2.5
VIL
Vcc=5V
GND
Unit
(Note 1)
The center frequency characteristics of BPF are determined by the
resistor connected between 3pin terminal and GND.If it is necessary,adjust the resistor value(note:all bands will be shifted
together).
The Q of BPF is fixed in 3.5 by inside circuit.
(Note 2)
The internal output resistor of peak hold output(PIN 15)is 10kW
typ.
The input resistance of the microprocessor must be much larger
than 10k W .
(Note 3)
The control voltage from the microprocessor must be from GND
-0.3V to Vcc+0.3V.
If the control voltage is out of the above range.
It`s necessary to modify the control voltage in the above range by
using resistors or diodes.
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OUTPUT CONTROL SPECIFICATION
<Output select logic table>
PHout
(PinNo.15)
ENB
SELA
SELB
SELC
GND(output stop)
0
X
X
X
GND
1
0
0
0
f1:105Hz
1
0
0
1
f2:340Hz
1
0
1
0
GND
1
0
1
1
f3:1kHz
1
1
0
0
GND
1
1
0
1
f4:3.4kHz
1
1
1
0
f5:10.5kHz
1
1
1
1
Note
X:Don`t Care
<Note 1>
'H'=low level,'1'=high level,'X'='0'or'1'
<Note 2>
The output setting time is more than 10µsec.
(When the output setting time is short,the output value and reset
signal become unstable)
90%
PHout
Ts(10µSec.MAX)
fn SELECT
(internal signal)
<SELECT state>
<Automatic Generation by
inside time constant>
fn RESET
(internal signal)
Tr(25µSec.TYP)
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TIMING CHART
H
ENB
L
H
SELA
X
X
X
X
X
X
L
H
SELB
L
H
SELC
L
PHout
f1
GND
f2
f3
f4
f5
H
f1 RESET
(105Hz)
L
H
f2 RESET
L
(340Hz)
H
f3 RESET
L
(1KHz)
H
f4 RESET
(3.4KHz)
L
H
f5 RESET
(10.5KHZ) L
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ELECTRICAL CHARACTERISTICS
(Ta=25 C ,Vcc=5.0V,PHout(Pin.No.15)RL=1MΩ unless otherwise
noted.VAIN=-30dBV, f=1KHz,ENB(Pin.No.13)=1)
Parameter
Symbol
Condition
Icc
No signal,No select
(ENB,SELA,SELB,SELC=0)
Vo
f1 to f5 Measured at each output
(VAIN=-14dBV)
Output offset voltage
Vos
f1 to f5 Measured at each output
(No signal,ENB=0/1)
Logic input H level
VIH
Logic input L level
Circuit current
Maximum output level
Common-mode rejection ratio
Limits
Min
4.0
typ
Max
Unit
8
13
mA
V
4.7
30
60
mV
2.5
5.0
Vcc
+0.3
V
VIL
GND
-0.3
0
0.5
V
CMRR
25
50
dB
f1 output level
Vo1
f1(fin=80 to 130Hz)
0.5
1.0
1.70
V
f2 output level
Vo2
f2(fin=270 to 410Hz)
0.5
1.0
1.70
V
f3 output level
Vo3
f3(fin=0.8 to 1.2KHz)
0.5
1.0
1.70
V
f4 output level
Vo4
f4(fin=2.7 to 4.1KHz)
0.5
1.0
1.70
V
f5 output level
Vo5
f5(fin=8.0 to 13.0KHz)
0.5
1.0
1.70
V
Ts
The time from the rise of output
selection until the rise of PHout
(90% of peak)
5
10
Output response time
µsec
<Reference>
Discharge level
DS
Inside reset signal
Tr=25µsecTYP.
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TEST CIRCUIT
Vcc/2
Vcc/2 Gen.
1
16
GND2
0.1m
PHOUT
VREF
2
0.1m
15
SELECTOR
V REF Gen.
1M
IREF
I REF Gen.
3
100K
HOLD
OUTPUT
BPF IN
4
T
CIRCUIT
f1 BPF 1
P.HOLD
D
2K
f2 BPF 2
P.HOLD
BPF 3
P.HOLD
f4 BPF 4
P.HOLD
BPF 5
P.HOLD
12
f3
+
C
CN
F
6
f5
39K
Px4
ENB
5
100K
IN
CONTROL
Amp-
Amp-
0.47m
GND1
13
2K
+
COU
14
MCU I/F
DIFOUT
OUTPUT
CONTROL
(Vccx0.3)
Px3
SELC
11
Px2
SELB
AOU
<PEAK HOLD>
T
7
Amp-A
100K
0.47m
AIN
2K
+
10
Px1
SELA
HOLD C RESET
AN
Vcc
F
8
9
39K
0.01m
10m
Units resistance:W
capacitance:F
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APPLICATION EXAMPLE
Vcc/2
Vcc/2 Gen.
1
16
GND2
0.1µ
VREF
2
V REF Gen.
0.1µ
SELECTOR
PHOUT
(VccX0.3)
IREF
14
I REF Gen.
3
100K
HOLD
OUTPUT
BPF IN
DIFOUT
4
COU
T
P.HOLD
f2 BPF 2
P.HOLD
BPF 3
P.HOLD
AmpD
2K
Amp-
A/D
f3
f4 BPF 4
P.HOLD
BPF 5
P.HOLD
F
6
f5
270K/2
Px4
ENB
12
+
C
CN
0.47µ
f1 BPF 1
5
100K
GND1
13
2K
+
COM
15
Px3
SELC
MCU
11
Px2
SELB
<Common-mode Noise Rejection >
ground isolation
AOU
<PEAK HOLD>
T
7
2K
Amp-A
100K
+
0.047µ
CH1
CH2
Px1
SELA
HOLD C RESET
AN
Vcc
F
8
0.047µ
10
9
270K
0.01µ
270K
10µ
<Input Audio Signal>
Units resistance:Ω
capacitance:F
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OUTLINE
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