MITSUBISHI M62381FP

MITSUBISHI<Dig.Ana.INTERFACE>
M62381FP
8-BIT 8CH MULTIPLYING D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M62381FP is an integrated circuit semiconductor of
CMOS structure with 8 channels of built-in 8-bit resolution
multiplication type D-A converters.
The input data is a easy-to-use 3-wire serial transfer method
and it is able to cascading serial use with Do terminal.
This device is capable of 4 quadrant multiplication because
of built-in inverting type amplifier.
Vo3
1
24
Vo4
Vo2
2
23
VIN3
Vo1
3
22
VIN4
FEATURES
VIN2
4
21
VDD
•Digital data transfer method
3-wire 12-bit serial data transfer method(DI,CLK,LD)
•High pressure proof(VDD±5V)
•Short setting time
•Built-in reset terminal,all the buffer amplifier outputs
forces zero volts.
VIN1
5
20
DI
GND
6
19
VSS
RESET
7
18
Do
VIN5
8
17
CLK
VIN6
9
16
LD
Vo5
10
15
VIN8
Vo6
11
14
VIN7
Vo7
12
13
Vo8
APPLICATION
Signal gain control of DISPLAY-MONITOR or CTV.
Conversion from digital control data analog control data
for form-use and industrial equipment.
Automatic adjustment by combination with EEPROM and
micro-computer.
(replacement of conventional half-fixed resistor.)
Outline 24P2V-A
VDD
BLOCK DIAGRAM
21
DI
20
12-BIT SHIFT RESISTER
18
Do
16
LD
CLK 17
DECODER
7
RESET
3
Vo1
VIN1
5
GND
6
VIN2
4
CH2
2
Vo2
VIN3
23
CH3
1
Vo3
VIN4
22
CH4
24 Vo4
VIN5
8
CH5
10
VIN6
9
CH6
11 Vo6
CH7
12 Vo7
CH8
13
8-BIT D-A
CONVERTER
VIN7 14
VIN8
15
Vo5
Vo8
19
VSS
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MITSUBISHI<Dig.Ana.INTERFACE>
M62381FP
8-BIT 8CH MULTIPLYING D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Pin No.
20
18
17
16
Symbol
DI
Do
3
CLK
LD
Vo1
2
Vo2
1
Vo3
24
Vo4
10
11
12
13
21
19
6
Vo5
5
VIN1
4
23
22
VIN2
Function
Serial data input terminal
Serial data output terminal
Serial clock input terminal
When LD terminal level is "H",latch circuit data is load
8-bit resolution D-A converter output terminal
Vo6
Vo7
Vo8
VDD
Analog and digital common power supply terminal
VSS
Analog negative power supply terminal
GND
GND terminal
VIN3
8
VIN4
VIN5
9
14
VIN6
VIN7
15
VIN8
7
RESET
D-A converter reference input terminal
When RESET terminal level is "H",all D-A output terminal became "0V"
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MITSUBISHI<Dig.Ana.INTERFACE>
M62381FP
8-BIT 8CH MULTIPLYING D-A CONVERTER WITH BUFFER AMPLIFIERS
DIGITAL DATA FORMAT
LAST
LSB
FIRST
MSB
DAC DATA
DAC SELECT DATA
(1)DAC set up data
MSB
LSB
D7
0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
-VIN
D-A output
0
0
0
0
0
0
0
1
(1/128-1) X VIN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(127/128-1) X VIN
1
1
0
0
0
0
0
0
1
(129/128-1) X VIN
1
1
1
1
1
1
1
0
(254/128-1) X VIN
1
1
1
1
1
1
1
1
(255/128-1) X VIN
(128/128-1) X VIN
(2)DAC select data
LSB
MSB
D11
DAC selection
D9
D8
0
D10
0
0
0
Don‘t care
0
0
0
1
ch1 selection
0
0
1
0
ch2 selection
0
1
0
0
1
1
ch7 selection
1
1
0
0
0
1
ch8 selection
1
1
1
1
Don‘t care
Don‘t care
TIMING CHART (MODEL)
MSB
DI
D11
LSB
D10
D9
D1
D0
CLK
LD
RESET
D-A
OUTPUT
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M62381FP
8-BIT 8CH MULTIPLYING D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Supply voltage
VDD
VIN
Vss
VIN
Vo
Input voltage
Output voltage
Topr
Tstg
Operating temperature
Storage temperature
Digital input voltage
Analog negative supply voltage
Ratings
Unit
-0.3 to +6.0
-0.3 to +6.0
-6.0 to +3.0
Vss+0.3 to VDD-0.3
Vss+0.3 to VDD-0.3
V
V
V
V
V
-20 to +85
-40 to +125
°C
°C
ELECTRICAL CHARACTERISTICS
Digital part(VDD=+5V, VSS=-5V,VDD≥VIN≥Vss,GND=0V,Ta=-20 to +85°C,unless otherwise noted)
Symbol
Test conditions
Parameter
VDD
Supply voltage
IILK
Input leak current
VIL
VOL
Input low voltage
Input high voltage
Output low voltage
IOL=2.5mA
VOH
Output high voltage
IOH=-400µA
VIH
Min.
4.5
Limits
Typ.
Max.
5.0
5.5
V
10
µA
-10
VIN=0 to Vcc
Unit
0.2VDD
V
0.8VDD
V
V
0.4
VDD-0.4
V
Analog part(VDD=+5V, VSS=-5V,VDD≥VIN≥Vss,GND=0V,Ta=-20 to +85°C,unless otherwise noted)
Symbol
IIN
Test conditions
Parameter
Min.
D-A converter reference input current
VAO
Buffer amplifier output voltage range
IAO
RES
DNL
NL
EG
Buffer amplifier output current range
Resolution
Differential nonlinearity
Nonlinearity
Gain error
Limits
Typ.
0.2
IAO=±500µA
IAO=±1mA
VAO=VAOZERO+0.3 to VAOFULL-0.3
VDD-0.5≥VIN≥VSS+0.5
Max.
0.4
Unit
mA
VAOZERO
+0.15
VAOZERO
+0.3
VAOFULL
-0.15
VAOFULL
-0.3
V
-1.0
8
-1.0
-1.5
-3
1.0
mA
1.0
1.5
3
bit
LSB
LSB
%FS
Max
Unit
AC CHARACTERISTICS
Symbol
tCXL
tCXH
tCR
tCF
tDCH
tCHD
tCHL
Parameter
Test conditions
Clock "L"pulse width
Clock "H"pulse width
Clock rise time
Clock fall time
Data set up time
Data hold time
Min
200
200
Limits
Typ
200
200
30
60
200
tLDH
tLDC
tDo
LD set up time
LD hold time
LD "H" pulse width
Data output delay time
CL=100pF
tLDD
D-A output setting time
Without load
100
100
MITSUBISHI
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70
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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MITSUBISHI<Dig.Ana.INTERFACE>
M62381FP
8-BIT 8CH MULTIPLYING D-A CONVERTER WITH BUFFER AMPLIFIERS
TIMING CHART
tCXH
tCR
tCF
CLK
tCXL
DI
tDCH
tLDC
tCHD
tLDH
tCHL
LD
tLDD
D-A
OUTPUT
tDo
Do
OUTPUT
APPLICATION EXAMPLE
5V
21
VDD
VDD
VSS
5
VIN1
4
VIN2
23 VIN3
Vo1
3
22 VIN4
Vo2
2
8
VIN5
Vo3 1
9
VIN6
Vo4 24
14 VIN7
Vo5 10
15 VIN8
Vo6 11
ANALOG OUT
Vo7 12
16 LD
Vo8 13
MICRO
COMPUTER
17 CLK
20
DI
7
RESET
GND
6
VSS
19
-5V
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