MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M62361FP is a Bi-CMOS semiconductor IC,containing 6 channels of 8-bit D-A converters(DAC),with a buffer operational amplifier provided in the output of each channel.It is easy to use due to serial data input, and three-pin(DT,CK,ST)connection with microcomputer. This IC is designed to be operable when chip select data contained in the 15-bit data conforms to the state of the CS terminal.Accordingly,the IC can process data by strobe signals common with other devices connected to the bus of microcomputer, and does not involve an microcomputer port to drive the IC.The inputs are connected to a level shift circuit so that the input threshold level does not depend on supply voltage.The IC also contains an initialization function to reset output(0 scale)when power is turned ON or drops. DK 1 16 VDD CK 2 15 Ao1 ST 3 14 Ao2 CS 4 13 Ao3 NC 5 12 Ao4 D.G 6 11 Ao5 A.G 7 10 Ao6 Vss 8 9 VREF Outline 16P2N-A NC:NO CONNECTION FEATURES •Output buffer operational amplifier provided in each channel •15-bit serial data input •6 channels of R-2R and segment type 8-bit DAC •Chip select terminal •Power-on reset function APPLICATION Digital-analog conversion in industrial or home-use electric equipment. Automatic control in combination with EEROM and microcomputer(Substitute for conventional semi-fixed resistor) Signal gain setting of display monitor and CTV. BLOCK DIAGRAM DT 16 VDD 1 15-BIT SHIFT RESISTER CK 2 ST 3 CS 4 LEVEL SHIFT 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4 RESET CIRCUIT 8 COMPARATOR DECODER 6 9 VREF 8-BIT LATCH 8-BIT LATCH 8-BIT LATCH 8-BIT LATCH 8-BIT LATCH 8-BIT LATCH 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 8-BIT DAC 15 Ao1 D.G 14 13 12 11 10 Ao2 Ao3 Ao4 Ao5 Ao6 MITSUBISHI ELECTRIC 8 VSS 7 A.G ( 1 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. 1 2 3 4 16 6 7 9 8 15 14 13 12 Function Symbol DT CK ST CS VDD D•G Serial data input terminal Shift clock input terminal to input data at rise of clock pulse Strobe input terminal to latch data in the register when H-level signal is input Chip select terminal Power supply terminal for input level shift circuit and buffer amplifier GND terminal for digital line GND terminal for analog line A•G VREF 8-bit D-A converter power supply terminal 8-bit D-A converter minimum power supply terminal Vss Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 NC 11 10 5 8-bit D-A converter output terminal Not used TIMING CHART (MODEL) LSB DT D01 D02 D03 D04 D02 D03 D04 CK ST AO MITSUBISHI ELECTRIC ( 2 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATINGS(Ta=25°C, unless otherwise noted) Symbol VDD VREF VIN Ao Pd K Topr Tstg Conditions Parameter Supply voltage Reference voltage Input voltage Output voltage Power dissipation Thermal derating Operating temperature Storage temperature Ratings Unit -0.3~+15 -0.3~+8 V V V V mW mW/°C -0.3~VDD -0.3~VDD 550 5.5 -20~+85 °C °C -55~+125 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS( Ta=25°C,VDD=8.0V,VREF=5.0V,Vss=0V,RL=2kΩ unless otherwise noted) Symbol Min. Limits Typ. Max. 6.0 8.0 14.0 V 5 10 mA 7.5 V 0.0 1.0 V 1.5 3 mA 8 bit -1.5 1.5 1.5 LSB Monotony assured -1.0 1 LSB -3 3 LSB H-level VDD=6.0 ~ 10V 3.5 VDD V L-level VDD=6.0 ~ 10V 0 H-level VDD=6.0 ~ 10V VDD=6.0 ~ 10V 1.0 10 µA 10 µA Test conditions Parameter VDD Operating supply voltage Ta=-25 ~ +85°C IDD Current dissipation Set at VREF Voltage range at VREF VREF=VDD-2V Vss RSL Resolution EZR EFS Zero point error DNL Differential nonlinearity error ECH Error between channels IIH IIL 4.0 Voltage range at Vss Maximum sink current at VREF VIL for all channels. RL=∞ -0.2 IREF VIH 128 256 Set at 107 256 for all channels. Vss≥0.3V -1.5 Full scale error Input voltage Input current L-level VAO Output voltage range Isink Output sink current Set at Output source current For FSR*,Ao≥FSR-2LSB Isource SR Output through rate VS1 Reset detection voltage 1 Hysteresis voltage 1 ∆VS1 VS2 ∆VS2 Reset detection voltage 2 Hysteresis voltage 2 0 -1.5 min. for all channels. V V -2LSB 0 100 µA -5 0 mA 0.3 V/µs Detection of VDD power 4.25 4.45 Detection of VDD power Detection of VREF power 0.05 Detection of VREF power LSB VREF 0.3 15 256 Unit 0.1 4.65 0.2 V V 2.85 3.0 3.15 V 0.03 0.06 0.15 V (*Full scale range = maximum output voltage setting) MITSUBISHI ELECTRIC ( 3 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS AC CHARACTERISTICS( Ta=25°C,VDD=8.0V,VREF=5.0V,Vss=0V,RL=2kΩ unless otherwise noted) Parameter Symbol tCKL tCKH tCR tCF tDCH tCHD tCHS tSTC tSTH tSTD Test conditions Min 200 200 Clock "L"pulse width Clock "H"pulse width Clock rise time Clock fall time Data set up time Data hold time Limits Typ Max 200 200 300 200 500 ST set up time ST hold time 500 500 ST "H" pulse width Ao output setting time 0 FSR FSR 20 0 Unit ns ns ns ns ns ns ns ns ns µs TIMING CHART tCKH tCR tCF CK tCKL DT tDCH tSTC tCHD tSTH tCHS ST tSTD Ao MITSUBISHI ELECTRIC ( 4 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS DESCRIPTION OF OPERATION 1.Level shift circuit The logical operation in the IC is controlled by VREF voltage. Therefore,the logical level of input is shifted to DG(Low)or VREF(High),regardless of fluctuating VDD. 2.15-bit shift register Data necessary for setting DAC is serially input.The data is input at positive edge of CK signal.The register is capable of retaining 15-bit data consisting of 3 blocks:DAC data.DAC select data and chip select data. (1)15 bit serial data (LSB) 1 2 3.Decoder(DAC select decoder) Appropriate one of the 6 DAC channels is selected by the 3bit DAC select data:S01,S02,S03. S01 S02 S03 0 0 0 VOUT 1 1 0 0 2 0 1 0 3 1 0 1 0 1 4 1 6 1 1 not select 1 1 not select 0 0 1 (MSB) 9 8 10 11 12 13 14 15 DATA 0 1 5 4.Comparator(Chip select data) Whether DAC data is effective or not is determined by the 4-bit data(C01 ~ C04)and the logic at CS terminal.Either of the following data combination is required. CK (2)Data allocation (LSB) (MSB) :DAC SETTING DATA :DAC SELECT DATA C02 C03 C04 CS 0 0 1 1 0 0 0 1 0 1 5.8-bit latch circuit When the data input to shift register meets the above requirement for comparator,D01~D08 data are latched in the channel selected by decoder.This data latching takes place when input at ST terminal is HIGH. :CHIP SELECT DATA 6.8-bit DAC + buffer amplifier Potential difference between VREF and Vss is output with 8bit resolution,using the R-2R system.No resolution is obtained for bit data lower than the output saturated voltage of the buffer amplifiers data lower than the output saturated voltage of the buffer amplifiers of analog output A01 to A06.The minimum value of 300mA,given for the electrical 5 Ao= C01 characteristic concerning output voltage range(VAO),indicates that no resolution is secured for output lower than 300mV. For all bit data,resolution is secured when Vss is operated with 300mV or higher voltage. 6 7 2 0 X D01 + 2 1 X D02 + 22 X D03 + 2 3 X D04 + 24 X D05 + 2 X D06 + 2 X D07 + 2 X D08 • (VREF - Vss) + Vss 256 MITSUBISHI ELECTRIC ( 5 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS DAC SETTING DATA(VREF=5.0V,Vss=0V) (LSB) (MSB) C01 C02 C03 C04 C05 C06 C07 C08 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF VREF X X (16/256) (17/256) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VREF VREF X X (254/256) (255/256) 7.Reset circuit This circuit monitors VDD and VREF,ensuring stable analog output when power is turned ON or OFF.If either input is abnormal,the reset circuit causes output buffer amplifiers to stop operation to retain the output in Vsat state,as well as resetting DAC data(0 scale)of all channels. A01~A06 0 Vsat (15/256) If VREF drops earlier than VDD,the analog output reset operation starts at point A. RESET TIMING CHART 4.45 VDD 4.5 DETECTED (HYSTERESIS VOLTAGE:100mV) VREF 3.06 (3.0V) 3.0 DETECTED (HYSTERESIS VOLTAGE:60mV) A AO t ALLOWABLE RANGE FOR SETTING OUTPUT MITSUBISHI ELECTRIC ( 6 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS APPLICATION EXAMPLE VDD=14V max REGULATOR 16 VREF= 7.5V max VDD 9 MICRO COMPUTER VREF 15 ch1 Ao2 14 ch2 Ao1 1 DT Ao3 13 ch3 2 CK Ao4 12 ch4 3 ST Ao5 11 ch5 4 CS Ao6 ch6 D.G A.G 6 7 10 Vss 8 Vss=0.3~1.0V When 8 pin is GND,Ao output is 0.3~VREF-1 LSB When 8 pin is Vss,Ao output is Vss~VREF-1 LSB MITSUBISHI ELECTRIC ( 7 / 8 ) MITSUBISHI<Dig.Ana.INTERFACE> M62361FP 8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS TYPICAL CHARACTERISTICS(Ta=25°C,VDD=8.0V,VREF=5.0V,RL=2kΩ,unless otherwise noted) CURRENT DISSIPATION VS. AMBIENT TEMPERATURE 8 VREF SINK CURRENT VS. AMBIENT TEMPERATURE 1.8 7 1.7 6 1.6 5 1.5 4 1.4 3 1.3 2 -20 0 20 40 60 80 1.2 -20 100 AMBIENT TEMPERATURE Ta(°C) 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(°C) RESET DETECTION VOLTAGE 1 VS. AMBIENT TEMPERATURE RESET DETECTION VOLTAGE 2 VS. AMBIENT TEMPERATURE 4.6 3.1 4.5 3.0 4.4 2.9 4.3 -20 0 20 40 60 80 -20 100 40 60 80 100 DIFFERENTIAL NONLINEARITY ERROR NONLINEARITY ERROR 0.50 0.50 0.40 0.40 0.30 0.30 0.20 0.20 0.10 0.10 -0.00 -0.00 -0.10 -0.10 -0.20 -0.20 -0.30 -0.30 -0.40 -0.40 -0.50 40 20 AMBIENT TEMPERATURE Ta(°C) AMBIENT TEMPERATURE Ta(°C) 0 0 -0.50 80 120 160 200 240 280 0 40 80 120 160 200 240 280 DATA DATA MITSUBISHI ELECTRIC ( 8 / 8 )