Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM PIN CONFIGURATION ( TOP VIEW ) DESCRIPTION The MH1V36CAM is an 1M word by 36-bit dynamic RAM module and consists of 2 industry standard 1M X 16 dynamic RAMs in TSOP and 1 industry standard 1M X 4(4CAS) dynamic RAMs in TSOP. The ICs are mounted on both sides of one small ceracom PC board with flash gold plating and form a convenient 68-pin package. FEATURES Type name Address OE RAS CAS Cycle access access access access time time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) MH1V36CAM-6 60 15 30 15 110 MH1V36CAM-7 70 20 35 20 130 Utilizes industry standard 1M X 16 DRAMs in TSOP package and industry standard 1M X 4(4CAS) DRAM in TSOP package Single 3.3V +/- 0.3V supply Low stand-by power dissipation 9mW (Max) . . . . . . . . . . . . . . . . . CMOS lnput level Low operating power dissipation MH1V36CAM - 6 . . . . . . . . . . . . . . . . 1.37W (Max) MH1V36CAM - 7 . . . . . . . . . . . . . . . . 1.20W (Max) All inputs, output TTL compatible and low capacitance 1024 refresh cycles every 16.4ms (A0 ~ A9) Includes 2pcs 0.22uF decoupling capacitors APPLICATION Main memory unit for computers, Microcomputer memory, Refresh memory for CRT MIT-DS-0027-0.0 DQ1 1 DQ2 2 DQ3 3 DQ4 4 DQ5 5 Vss 6 DQ6 7 DQ7 8 DQ8 9 DQP1 10 DQ9 11 Vcc 12 DQ10 13 DQ11 14 DQ12 15 DQ13 16 DQ14 17 Vss 18 DQ15 19 DQ16 20 DQP2 21 Vcc 22 /CAS0 23 /CAS3 24 A0 25 A1 26 A2 27 Vss 28 A3 29 A4 30 A5 31 /RAS 32 A6 33 Vcc 34 MITSUBISHI ELECTRIC ( 1 / 18 ) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 DQP4 DQ32 DQ31 DQ30 DQ29 Vss DQ28 DQ27 DQ26 DQ25 DQP3 Vcc DQ24 DQ23 DQ22 DQ21 DQ20 Vss DQ19 DQ18 DQ17 Vcc /CAS2 /CAS1 /W /OE RFU(NC) Vss RFU(NC) RFU(NC) A9 A8 A7 Vcc 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM FUNCTION The MH1V36CAM provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, RAS-only refresh, and delayed-write. The input conditionsfor each are shown in Table 1. Table 1 Input conditions for each mode Inputs Input/Output Operation RAS CAS W OE Read ACT ACT NAC ACT Row address APD Column address APD Write (Early write) ACT ACT ACT DNC APD APD Write (Delayed write) ACT ACT ACT DNC APD Read-modify-write ACT ACT ACT ACT RAS-only refresh ACT NAC DNC DNC Hidden refresh ACT ACT DNC CAS before RAS refresh ACT ACT Standby NAC DNC Refresh Input Output OPN VLD YES VLD OPN YES APD VLD IVD YES APD APD VLD VLD YES APD DNC DNC OPN YES ACT APD DNC OPN VLD YES NAC DNC DNC DNC DNC OPN YES DNC DNC DNC DNC DNC OPN NO Remark Fast page mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open BLOCK DIAGRAM Add /W /OE /CAS3 /CAS2 /CAS1 /CAS0 /RAS 25,26,27,29,30,31,33,36,37,38 44 43 24 46 45 23 32 /RAS /UCAS /LCAS /OE /W Add /RAS M5M4V18160C /UCAS /LCAS /OE /W Add M5MV18160C /RAS /CAS1 /CAS3 /OE /CAS2 /CAS4 /W Add M5M4V4500C DQ1 DQ2 DQ3 DQ4 68 58 21 10 DQP4 DQP3 DQP2 DQP1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 11 13 14 15 16 17 19 20 01 02 03 04 05 07 08 09 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 48 49 50 52 53 54 55 56 59 60 61 62 64 65 66 67 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 C1 to C2 0.22 uF 12 22 34 35 47 57 Vcc MIT-DS-0027-0.0 6 18 28 41 51 63 Vss MITSUBISHI ELECTRIC ( 2 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI V0 I0 Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ta=25°C RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vss VIH VIL Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 3 0 ~ 70 -40 ~ 100 Parameter (Ta=0 ~70 °C Min 3.0 0 2.0 -0.3 Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Limits Nom 3.3 0 Unit V V V mA W °C °C , unless otherwise noted) (Note 1) Max 3.6 0 Vcc+0.3 0.8 Unit V V V V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol VOH VOL IOZ II Parameter Test conditions High-level output voltage Low-level output voltage Off-state output current Input current Average supply ICC1 (AV) current from Vcc operating (Note 3,4,*) ICC2 (Ta=0 ~70 °C, Vcc=3.3V+/- 0.3V, Vss=0V, unless otherwise noted) (Note 2) IOH=-2.0mA IOL=2.0mA Q floating 0V≤VOUT≤3.3V 0V≤VIN≤3.6V, Other inputs pins=0V -6 -7 Supply current from Vcc , stand-by Average supply current ICC3 (AV) from Vcc refreshing (Note 3,*) Average supply current from Vcc ICC4(AV) Fast-Page-Mode (Note 3,4,*) Average supply current from Vcc ICC6(AV) CAS before RAS refresh (Note 3,5,*) mode Min 2.4 0 -10 -30 -6 -7 -6 -7 -6 -7 Limits Typ Max Vcc 0.4 10 30 RAS, CAS cycling tRC=tWC=min. output open 380 RAS= CAS =VIH, output open RAS= CAS≥Vcc -0.2V, output open 6 1.5 RAS cycling, CAS= VIH tRC=min. output open 380 RAS=VIL, CAS cycling tPC=min. output open 210 CAS before RAS refresh cycling tRC=min. output open 370 Unit V V mA 330 mA mA 330 mA 190 mA 320 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. *: Column Address can be channged once or less while RAS=VIL and LCAS/UCAS=VIH CAPACITANCE Symbol (Ta=0~70°C , Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted) Parameter Input capacitance, address inputs CI (OE) Input capacitance, OE input CI (W) Input capacitance, write control input CI (RAS) Input capacitance, RAS input CI (CAS) Input capacitance, CAS input CI / O Input/Output capacitance, data ports Test conditions CI (A) MIT-DS-0027-0.0 VI=Vss f=1MHZ Vi=25mVrms MITSUBISHI ELECTRIC ( 3 / 18 ) Min Limits Typ Max Unit 50 pF 55 55 55 50 40 pF pF pF pF pF 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~70°C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 5,12,13) Limits Symbol Parameter -6 Min -7 Max Min Unit Max tCAC Access time from CAS (Note 6,7) 15 20 ns tRAC Access time from RAS (Note 6,8) 60 70 ns tAA Columu address access time (Note 6,9) 30 35 ns tCPA Access time from CAS precharge (Note 6,10) 35 40 ns tOEA Access time from OE (Note 6) 15 20 ns tCLZ Output low impedance time from CAS low (Note 6) tOFF Output disable time after CAS high tOEZ Output disable time after OE high (Note 11) (Note 11) ns 5 5 0 15 0 20 ns 0 15 0 20 ns Note 5: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS clock such as RAS-Only refresh). Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 16.4 ms) of RAS inactivity before proper device operation is achieved. 6: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF. The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL). 7: Assumes that tRCDÅD≥tRCD(max) and tASC ≥tASC(max). 8: Assumes that tRCD ≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 9: Assumes that tRAD ≥tRAD(max) and tASC≤tASC(max). 10: Assumes that tCP ≤tCP(max) and tASC≥tASC(max). 11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT ≤I +/- 10uAI) and is not reference to VOH(min) or VOL(max). TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles) (Ta=0 ~ 70 °C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 12,13) Limits Symbol -6 Parameter Min -7 Max Min 16.4 Unit Max tREF Refresh cycle time tRP RAS high pulse width tRCD Delay time, RAS low to CAS low tCRP Delay time, CAS high to RAS low 10 10 ns tRPC Delay time, RAS high to CAS low 0 0 ns tCPN CAS high pulse width 10 10 tRAD Column address delay time from RAS low tASR Row address setup time before RAS low tASC Column address setup time before CAS low tRAH Row address hold time after RAS low 10 10 ns tCAH Column address hold time after CAS low 15 15 ns tDZC Delay time, data to CAS low (Note17) 0 0 ns tDZO Delay time, data to OE low (Note17) 0 ns tCDD Delay time, CAS high to data (Note18) 15 0 20 tODD Delay time, OE high to data (Note18) 15 20 tT Transition time (Note19) 1 40 (Note14) (Note15) 20 15 45 30 0 (Note16) 0 16.4 20 15 50 50 0 1 ns ns 35 ns ns 0 10 ms ns 50 10 ns ns ns 50 ns Note 12: The timing requirements are assumed tT =5ns. 13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min). 15: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA. 16: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by tCAC. 17: Either tDZC or tDZO must be satisfied. 18: Either tCDD or tODD must be satisfied. 19: tT is measured between VIH(min) and VIL(max). MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 4 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Read and Refresh Cycles Limits Symbol -6 Parameter Min -7 Max Min 110 Unit Max tRC Read cycle time tRAS RAS low pulse width 60 10000 130 70 10000 ns ns tCAS CAS low pulse width 15 10000 20 10000 ns tCSH CAS hold time after RAS low 60 70 ns tRSH RAS hold time after CAS low 15 20 ns tRCS Read Setup time after CAS high 0 0 ns tRCH Read hold time after CAS low (Note 20) Read hold time after RAS low (Note 20) 0 10 ns tRRH 0 10 tRAL Column address to RAS hold time 30 35 ns tOCH CAS hold time after OE low 15 20 ns tORH RAS hold time after OE low 15 20 ns ns Note 20: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle (Early Write and Delayed Write) Limits Symbol Parameter -6 Min -7 Max Min Unit Max tWC Write cycle time tRAS RAS low pulse width 60 10000 70 10000 ns tCAS CAS low pulse width 15 10000 20 10000 ns tCSH CAS hold time after RAS low 60 70 ns tRSH RAS hold time after CAS low 15 20 ns tWCS Write setup time before CAS low 0 0 ns tWCH Write hold time after CAS low 10 15 ns tCWL CAS hold time after W low 15 20 ns tRWL RAS hold time after W low 15 20 ns tWP Write pulse width 10 15 ns tDS Data setup time before CAS low or W low 0 0 ns tDH Data hold time after CAS low or W low 10 15 ns tOEH OE hold time after W low 15 20 ns MIT-DS-0027-0.0 110 (Note 22) MITSUBISHI ELECTRIC ( 5 / 18 ) ns 130 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Read-Write and Read-Modify-Write Cycles Limits Symbol -6 Parameter Min -7 Max Min Unit Max tRWC Read write/read modify write cycle time (Note21) 155 tRAS RAS low pulse width 105 10000 120 10000 ns tCAS CAS low pulse width 60 10000 70 10000 ns tCSH CAS hold time after RAS low 105 120 ns tRSH RAS hold time after CAS low 60 70 ns tRCS Read setup time before CAS low 0 0 ns tCWD Delay time, CAS low to W low (Note22) 40 45 ns tRWD Delay time, RAS low to W low (Note22) 85 95 ns tAWD Delay time, address to W low (Note22) 55 60 ns tCWL CAS hold time after W low 15 20 ns tRWL RAS hold time after W low 15 20 ns tWP Write pulse width 10 15 ns tDS Data setup time before W low ÅÜ Data hold time after ÅÖ W low OE hold time after W low 0 0 ns 10 15 ns 15 20 ns tDH tOEH ÅÜ ÅÖ 180 ns Note 21: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+5tT. 22: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate. Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 23) Limits Symbol Parameter -6 Min -7 Max Min tPC Fast page mode read/write cycle time 40 45 tPRWC Fast page mode read write/read modify write cycle time 85 95 tRAS RAS low pulse width for read write cycle (Note24) tCP CAS high pulse width tCPRH RAS hold time after CAS precharge tCPWD Delay time, CAS precharge to W low (Note25) (Note22) Unit Max ns ns 100 100000 115 100000 ns 10 15 10 15 ns 35 40 ns 60 65 ns Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 24: tRAS(min) is specified as two cycles of CAS input are performed. 25: tCP(max) is specified as a reference point only. CAS before RAS Refresh Cycle (Note 26) Limits Symbol -6 Parameter Min -7 Max Min Unit Max tCSR CAS setup time before RAS low 10 10 ns tCHR CAS hold time after RAS low 10 15 ns tRSR Read setup time before RAS low 10 10 ns tRHR Read hold time after RAS low CAS low pulse width 10 15 ns 25 30 ns tCAS Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 6 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Timing Diagrams Read Cycle (Note 27) tRC tRAS RAS tRP VIH VIL tCSH tCRP CAS tRCD tRPC tRSH tCAS tCRP VIH VIL tASR VIH A0 ~ A9 tRAD tRAL tRAH ROW ADDRESS tASR tCAH tASC tCPN COLUMN ADDRESS ROW ADDRESS VIL tRRH tRCH tRCS W VIH VIL tDZC DQ (INPUTS) tCDD VIH Hi-Z VIL tCAC tAA tOFF tCLZ VOH DQ (OUTPUTS) VOL Hi-Z tRAC tOEZ tDZO OE Hi-Z DATA VALID tOEA tOCH tODD VIH VIL tORH Note 27 Indicates the don't care input. VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max) Indicates the invalid output. Indicates the skew of the four inputs. MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 7 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Write Cycle (Early write) tWC tRAS RAS tRP VIH VIL tCSH tCRP CAS tRCD tRSH tCAS tRPC tCRP VIH VIL tASR VIH A0 ~ A9 tASR tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS ROW ADDRESS VIL tWCS W tWCH VIH VIL tDS DQ (INPUTS) VIH DATA VALID VIL VOH DQ (OUTPUTS) VOL OE tDH Hi-Z VIH VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 8 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Write Cycle (Delayed write) tWC tRP tRAS RAS VIH VIL tCSH tCRP CAS tRPC tRSH tCAS tRCD tCRP VIH VIL tASR VIH A0 ~ A9 tRAH tCAH tASC tASR ROW ADDRESS COLUMN ADDRESS ROW ADDRESS VIL tCWL tRWL tWP tRCS W VIH VIL tWCH tDZC DQ (INPUTS) tDS VIH tDH DATA VALID Hi-Z VIL tCLZ VOH DQ (OUTPUTS) VOL Hi-Z Hi-Z tDZO tOEH tOEZ tODD OE VIH VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 9 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS RAS tRP VIH VIL tCSH tRCD tCRP CAS tCRP VIH VIL tRAD tASR VIH A0 ~ A9 tRAH tCAH tASC ROW ADDRESS tASR COLUMN ADDRESS VIL ROW ADDRESS tAWD tCWD tRWD tRCS W tRPC tRSH tCAS tCWL tRWL tWP VIH VIL tDH tDS tDZC DQ (INPUTS) VIH Hi-Z VIL DATA VALID tCAC tAA tCLZ VOH DQ (OUTPUTS) VOL DATA VALID Hi-Z tRAC tODD tDZO OE Hi-Z tOEA tOEZ tOEH VIH VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 10 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS RAS tRP VIH VIL tRPC tCRP tCRP VIH CAS VIL tASR VIH A0 ~ A9 VIL W tRAH tASR ROW ADDRESS ROW ADDRESS VIH VIL DQ (INPUTS) VIH VIL VOH DQ (OUTPUTS) VOL OE Hi-Z VIH VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 11 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM CAS before RAS Refresh Cycle tRC tRP RAS tRC tRAS tRAS tRP VIH VIL tRPC CAS tCSR tCHR tRPC tCSR tCHR tRPC tCRP VIH VIL tCPN tASR VIH ROW ADDRESS A0 ~ A9 VIL tRCH tRSR tRHR tRSR tRHR COLUMN ADDRESS tRCS VIH W DQ (INPUTS) VIL VIH VIL tOFF VOH DQ (OUTPUTS) VOL Hi-Z tOEZ VIH OE VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 12 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 28) tRC tRC tRAS RAS tRP tRAS tRP VIH VIL tCRP tRCD tRSH tCHR VIH CAS VIL tRAD tASR VIH tRAH tASC ROW ADDRESS A0 ~ A9 tASR tCAH COLUMN ADDRESS ROW ADDRESS VIL tRCS tRRH tRAL W VIH VIL tDZC DQ (INPUTS) tCDD VIH Hi-Z VIL tCAC tAA tCLZ VOH DQ (OUTPUTS) VOL tOFF Hi-Z tRAC tDZO Hi-Z DATA VALID tOEZ tOEA tORH tODD VIL OE VIH Note 28: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 13 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Fast Page Mode Read Cycle tRAS RAS tRP VIH VIL tCSH tCRP CAS tPC tRCD tCAS tCP tCAS tRSH tCAS tCP VIH VIL tCPRH tRAD tASR A0 ~ A9 VIH tRAH tASC ROW ADDRESS tASC tCAH COLUMN-1 tASC tCAH COLUMN-2 tCAH tASR ROW ADDRESS COLUMN-3 VIL tRAL tRCS W tRCS tRCH tRCH tRCS tRRH tRCH VIH VIL tDZC DQ (INPUTS) tDZC tDZC tCDD VIH Hi-Z tCAC Hi-Z tCAC VIL tAA tAA tOFF tCLZ VOH DQ (OUTPUTS) VOL tCLZ DATA VALID-1 Hi-Z tRAC tDZO tCAC tAA tOFF tCLZ DATA VALID-2 DATA VALID-3 tCPA tOEA tOCH tOEZ tOFF tCPA tOEA tOCH tOEZ tOEA tOCH tOEZ VIL OE VIH tDZO tODD MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 14 / 18 ) tDZO tODD tODD tORH 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Fast Page Mode Write Cycle (Early Write) tRAS RAS tRP VIH VIL tCSH tCRP CAS tRCD tPC tCAS tCP tRSH tCAS tCP tCAS VIH VIL tASR VIH A0 ~ A9 tRAH ROW ADDRESS tCAH tASC tCAH tASC COLUMN-1 COLUMN-2 tCAH tASC COLUMN-3 VIL W tWCS tWCH tWCS tWCH tDS tDH tDS tDH tWCS tASR ROW ADDRESS tWCH VIH VIL DQ (INPUTS) VIH VIL VOH DQ (OUTPUTS) VOL DATA VALID-1 DATA VALID-2 tDS tDH DATA VALID-3 Hi-Z VIH OE VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 15 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Fast-Page Mode Write Cycle (Delayed Write) tRAS RAS tRP VIH VIL tCSH tCRP tRCD tRSH tPC tCAS tCAS tCP CAS VIH VIL tASR A0 ~ A9 VIH tRAH tCAH tASC ROW ADDRESS tASC COLUMN-1 tCAH tRWL tCWL tASR ROW ADDRESS COLUMN-2 VIL tCWL tRCS tRCS tWP W tWP VIH VIL tWCH tDZC DQ (INPUTS) VIH DQ (OUTPUTS) VOH tWCH tDH tDS DATA VALID-1 Hi-Z VIL tCLZ tDZC tDS tDH DATA VALID-2 Hi-Z tCLZ Hi-Z Hi-Z Hi-Z VOL tDZO tOEZ tOEZ tODD tDZO tODD tOEH VIH OE VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 16 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM Fast Page Mode Read-Write,Read-Modify-Write Cycle tRAS RAS tRP VIH VIL tCSH tCRP tRWL tRCD tPRWC tCAS tCP CAS tCAS VIH VIL tRAD tASR VIH A0 ~ A9 tRAH ROW ADDRESS tASC tCAH tASC COLUMN-1 tCAH tCWL tASR ROW ADDRESS COLUMN-2 VIL tAWD tRCS tAWD tCWL tCWD tCWD tRCS tWP W tWP VIH VIL tRWD tCPWD tDZC DQ (INPUTS) VIH tDZC tDS DATA VALID-1 Hi-Z tCAC VIL tDH tDS tAA tAA tCLZ DATA VALID-1 Hi-Z tRAC tDZO DATA VALID-2 Hi-Z tCAC tCLZ VOH DQ (OUTPUTS) VOL tDH DATA VALID-1 Hi-Z tCPA tODD tOEA tOEZ Hi-Z tODD tDZO tOEZ tOEH tOEA VIH OE VIL MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 17 / 18 ) 21 May 1996 Preliminary Spec. MITSUBISHI LSIs Some of contents are subject to change without notice. MH1V36CAM-6,-7 FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM MH1V36CAM OUTLINE No mounted area 11mm x 11mm 58 3.5MAX 10.5 29 68 35 24 21 11mm A 11mm 1 34 1 33 x 1 = 33 1 12.5 1.2 1 0.5 :0°~5° 1.0 1.5 2.55 Detail A MIT-DS-0027-0.0 MITSUBISHI ELECTRIC ( 18 / 18 ) 21 May 1996