MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM DESCRIPTION PIN CONFIGURATION The MH32V7245BST is 33554432-word x 72-bit dynamic ram stacked structural module. This consist of thirty-six industry standard 16M x 4 dynamic RAMs in TSOP and two industry standard input buffer in TSSOP. The stacked structure of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module. FEATURES Type name /RAS /CAS Address /OE access access access access time time time time Cycle Power time dissipation (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) 85pin 1pin 94pin 10pin 95pin 11pin 124pin 40pin 125pin 41pin 168pin 84pin (typ.W) MH32V7245BST-5 50 18 30 18 84 7.03 MH32V7245BST-6 60 20 35 20 110 5.87 Utilizes industry standard 16M x 4 RAMs TSOP and industry standard input buffer in TSSOP 168-pin (84-pin dual dual in-line package) stacked structure Single 3.3V(+/- 0.3V) supply operation Low stand-by power dissipation . . . . . . . . . . 64.9mW(Max) Low operation power dissipation MH32V7245BST -5 . . . . . . . . . . . . . . . . . . 8.44W(Max) MH32V7245BST -6 . . . . . . . . . . . . . . . . . . 7.79W(Max) All input are directly LVTTL compatible All output are three-state and directry LVTTL compatible Includes(0.22 uF x 38) decoupling capacitors 4096 refresh cycle every 64ms (A0 - A11) Hyper-page mpde,Read-modify-write,/CAS before /RAS refresh, Hidden refresh capabilities JEDEC standard pin configration & Buffered PD pin Buffered input except /RAS and DQ Gold plating contact pads FRONT SIDE BACK SIDE APPLICATION Main memory unit for computers , Microcomputer memory PD&ID TABLE -5 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 0 0 0 1 0 0 0 1 0 0 -6 1 0 0 0 1 1 1 0 0 0 -7 1 0 0 0 1 0 1 0 0 0 1 = NC , 0 = drive to VOL PD pin . . . buffered. When /PDE is low, PD information can be read ID pin . . . non-buffered 1 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM PIN CONFIGURATION Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss Reserved Reserved Vcc /WE0 /CAS0 Reserved /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 Reserved Vcc RFU RFU 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Vss /OE2 /RAS2 /CAS4 Reserved /WE2 Vcc Reserved Reserved DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss PD1 PD3 PD5 PD7 ID0 Vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss Reserved Reserved Vcc RFU /CAS1 Reserved /RAS1 RFU Vss A1 A3 A5 A7 A9 A11 Reserved Vcc RFU B0 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Vss RFU /RAS3 /CAS5 Reserved /PDE Vcc Reserved Reserved DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss PD2 PD4 PD6 PD8 ID1 Vcc Reserved: Reserved use RFU: Reserved for future use 2 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM BLOCK DIAGRAM /RAS0 /CAS0 /RAS2 /CAS4 /RAS1 /RAS3 /CAS1 /CAS5 /WE0 /WE2 /OE0 /OE2 /OE /W /CAS D0 /OE /W /CAS D1 /OE /W /CAS D2 /OE /W /CAS D3 /OE /W /CAS D4 /OE /W /CAS D5 /OE /W /CAS D6 /OE /W /CAS D7 /OE /W /CAS D8 /RAS /OE DQ1 ~DQ4 /RAS /OE /OE /OE /OE /OE /OE /CAS /W /CAS /W /CAS /W /CAS D24 /OE DQ1 ~DQ4 /RAS /W D23 DQ1 ~DQ4 /RAS /CAS D22 DQ1 ~DQ4 /RAS /W D21 DQ1 ~DQ4 /RAS /CAS D20 DQ1 ~DQ4 /RAS /W D19 DQ1 ~DQ4 /RAS /CAS D18 DQ1 ~DQ4 /RAS /W /W /CAS D25 /OE DQ1 ~DQ4 /W /CAS D26 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 DQ0 DQ1 DQ2 DQ3 /OE /W DQ4 DQ5 DQ6 DQ7 /OE /W DQ8 DQ9 DQ10 DQ11 /OE /W DQ12 DQ13 DQ14 DQ15 /OE /W DQ16 DQ17 DQ18 DQ19 /OE /W DQ20 DQ21 DQ22 DQ23 /OE /W DQ24 DQ25 DQ26 DQ27 /OE /W DQ28 DQ29 DQ30 DQ31 /OE /W DQ32 DQ33 DQ34 DQ35 /OE /W /CAS /RAS /OE DQ1 ~DQ4 D9 /CAS D10 /CAS D11 /CAS D12 /CAS D13 /CAS D14 /CAS D15 /CAS D16 /CAS D17 /RAS /OE /OE /OE /OE /OE /OE DQ1 ~DQ4 /CAS /W /CAS /W /CAS /W /CAS D33 /OE DQ1 ~DQ4 /RAS /W D32 DQ1 ~DQ4 /RAS /CAS D31 DQ1 ~DQ4 /RAS /W D30 DQ1 ~DQ4 /RAS /CAS D29 DQ1 ~DQ4 /RAS /W D28 DQ1 ~DQ4 /RAS /CAS D27 DQ1 ~DQ4 /RAS /W /W /CAS D34 /OE /W /CAS D35 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 /RAS DQ1 ~DQ4 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 D : M5M465405BTP A0 D0 - D8 D18 - D26 B0 D9 - D17 D27 - D35 A1 - A11 3 D0 - D35 MIT - DS - 0218-0.0 Stacked Unit Vcc C1. -. C . 20 D0 - D35 & INPUT BUFFER Vss MITSUBISHI ELECTRIC PIN NAME /RAS /CAS /WE /OE A, B DQ Vcc Vss FUNCTION ROW ADDRESS STROBE INPUT COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT ADDRESS INPUT DATA I/O POWER SUPPLY GROUND 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM FUNCTION The MH32V7245BST provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., hyper page mode, /CAS before /RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Inputs Input/Output Operation Refresh /OE Row address Column address Input /RAS /CAS /W Read ACT ACT NAC ACT APD APD OPN VLD NO Write (Early write) ACT ACT ACT DNC APD APD VLD OPN NO Write (Delayed write) ACT ACT ACT DNC APD APD VLD IVD NO Read-modify-write ACT ACT ACT ACT APD APD VLD VLD NO Hidden refresh ACT ACT DNC ACT DNC DNC OPN VLD YES /CAS before /RAS refresh ACT ACT NAC DNC DNC DNC DNC OPN YES Standby NAC DNC DNC DNC DNC DNC DNC OPN NO Remark Output Hyper page mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open 4 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc IO Pd Topr Tstg Parameter Supply voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ta=25°C (Ta=0~70°C, unless otherwise noted) (Note 1) RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vss VIH VIL Parameter Min 3.0 0 2.0 -0.3 Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Unit V mA W °C °C Ratings -0.5~4.6 50 20 0~70 -40~100 Limits Nom 3.3 0 Unit Max 3.6 0 Vcc+0.3 V V V 0.8 V Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Supply current from Vcc , stand-by ICC4(AV) Average supply current from Vcc Hyper-Page-Mode ICC6(AV) -6 -5 (Note 3,4,5) Average supply current from Vcc /CAS before /RAS refresh mode (Note 3,5) VOUT VII ICC2 -5 VII (Note 3,4,5) IOH=-2.0mA IOL=2.0mA Q floating 0V VII VII ICC1 (AV) High-level output voltage Low-level output voltage Off-state output current Input current (except /RAS) Input current (/RAS) Average supply current from Vcc operating Test conditions VII VII VOH VOL IOZ II I I (RAS) Parameter Vcc 0V VIN Vcc+0.3V, Other input pins=0V 0V VIN Vcc+0.3V, Other input pins=0V Min 2.4 0 -20 -10 -90 Limits Typ /RAS, /CAS cycling tRC=tWC=min. output open -6 -5 -6 Max Vcc 0.4 20 10 90 2378 Unit V V µA µA µA mA 2198 /RAS=/CAS =VIH, output open /RAS=/CAS Vcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open 56 38 IIV Symbol (Ta=0~70°C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted) (Note 2) 1838 mA mA 1658 /CAS before /RAS refresh cycling tRC=min. output open 2378 mA 2198 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH CAPACITANCE (Ta = 0~70°C, Vcc = 3.3V ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter CI (/RAS) Input capacitance, /RAS input CI Input capacitance, except /RAS input C(DQ) Input/Output capacitance,DATA 5 MIT - DS - 0218-0.0 Test conditions VI=Vss f=1MHZ Vi=25mVrms MITSUBISHI ELECTRIC Min Limits Typ Max 80 15 25 Unit pF pF pF 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits Symbol Parameter -5 Min tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Access time from /CAS (Note 7,8) Access time from /RAS (Note 7,9) Columu address access time (Note 7,10) Access time from /CAS precharge (Note 7,11) Access time from /OE (Note 7) Output hold time from /CAS Output hold time from /RAS (Note 13) Output low impedance time from /CAS low (Note 7) Output disable time after /OE high (Note 12) Output disable time after /WE high (Note 12) Output disable time after /CAS high (Note 12,13) Output disable time after /RAS high (Note 12,13) Unit -6 Max 18 50 30 33 18 Min Max 20 60 35 38 20 10 5 10 10 5 10 20 20 20 18 18 18 13 15 ns ns ns ns ns ns ns ns ns ns ns ns IIV IIV IIV Note 6: An initial pause of 500 us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /CAS before /RAS refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1TTL loads and 50pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA). The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD tRCD(max), tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT I +/- 10 uAI) and is not reference to VOH(min) or VOL(max). 13: Output is disable after both /RAS and /CAS go to high. VII VII IIV IIV VII VII VII TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles) (Ta=0~70°C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted ,see notes 14,15) Limits Symbol -6 -5 Parameter Min tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low tRDD tCDD tODD tT Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time 30 9 10 0 8 5 5 0 3 8 0 0 (Note16) (Note17) (Note18) (Note19) (Note19) 13 18 18 1 (Note20) (Note20) (Note20) (Note21) Max 64 32 20 10 50 Min 40 9 10 0 10 7 5 0 5 10 0 0 15 20 20 1 Unit Max 64 40 25 13 50 ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIT - DS - 0218-0.0 IIV IIV IIV 6 VII Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Read and Refresh Cycles Limits Symbol Parameter -5 -6 Min tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS iow Read Setup time after /CAS high Read hold time after /CAS iow Read hold time after /RAS iow Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE iow /CAS hold time after /OE iow (Note 22) (Note 22) 84 50 8 30 18 0 0 0 Max 10000 10000 Unit Min 104 60 10 43 20 0 0 0 30 13 18 13 Max ns ns ns ns ns ns ns ns ns ns ns ns 10000 10000 35 18 20 15 Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle (Early Write and Delayed Write) Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter -5 Write cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS low Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after W low Write pulse width Data setup time before /CAS low or W low Data hold time after /CAS low or W low (Note 24) Min 84 50 8 30 18 0 8 8 13 8 -5 13 Unit -6 Max 10000 10000 Min 104 60 10 35 20 0 10 10 15 10 -5 15 Max ns ns ns ns ns ns ns ns ns ns ns ns 10000 10000 Read-Write and Read-Modify-Write Cycles Limits Symbol -5 Parameter tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low tOEH OE hold time after W low (Note23) (Note24) (Note24) (Note24) Min 109 75 38 65 43 0 28 60 40 -6 Max 10000 10000 13 Min 133 89 44 77 49 0 32 72 47 Unit Max ns ns ns ns ns ns ns ns ns 10000 10000 15 ns 7 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC IIV IIV IIV IIV IIV Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeteminate. 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25) Limits Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter -5 Hyper page mode read/write cycle time Hyper page mode read write/read modify write cycle time Output hold time from /CAS low /RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time,/CAS precharge to /W low (Note26) (Note27) (Note24) Hold time to maintain the data Hi-Z until /CAS access /OE Pulse width(Hi-Z control) /W Pulse width(Hi-Z control) Delay time,/CAS low to /W low after read Delay time, Address to /W low after read Delay time,/CAS precharge to /W low after read Delay time,/CAS low to /OE high after read Delay time,Address to /OE high after read Delay time, /CAS precharge to /OE high after read Min 20 55 10 65 8 33 43 7 7 -6 Max Min 25 66 10 77 10 38 100000 15 Unit Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100000 16 50 7 7 7 28 40 43 13 25 28 7 32 47 50 15 30 33 Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only. /CAS before /RAS Refresh Cycle (Note 28) Limits Symbol Parameter -5 tCSR tCHR /CAS setup time before /RAS low /CAS hold time after /RAS low Min 10 5 tRSR tRHR Read setup time before /RAS low Read hold time after /RAS low 15 5 Unit -6 Max Min 10 5 15 5 Max ns ns ns ns Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode. 8 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Timing Diagrams Read Cycle (Note 29) tRC tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tCRP tRSH tCAS VIH / CAS VIL tRAL tCAL tRAD tASR A0,B0~A11 VIH VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS VIH /W VIL tCDD tDZC DQ (INPUTS) tRDD VIH Hi-Z VIL tREZ tCAC tAA tOHR tCLZ DQ (OUTPUTS) tWEZ tOFF tOHC VOH Hi-Z VOL Hi-Z DATA VALID tRAC tOEA tDZO tOEZ tODD tOCH VIH /OE VIL tORH VIN VII VII VII Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VII Note 29 VIL(max) Indicates the invalid output. 9 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Early Write Cycle tWC tRAS /RAS tRP VIH VIL tCSH tCRP tRCD tRSH tCAS tCRP VIH /CAS VIL tASR A0,B0~A11 VIH VIL tASR tRAH tCAH tASC ROW ADDRESS tWCS /W ROW ADDRESS COLUMN ADDRESS tWCH VIH VIL tDS DQ (INPUTS) DQ (OUTPUTS) tDH VIH DATA VALID VIL VOH Hi-Z VOL VIH /OE VIL 10 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Delayed Write Cycle tWC tRP tRAS /RAS VIH VIL tCSH tCRP tCRP tRSH tRCD tCAS VIH / CAS VIL tASR VIH A0,B0~A11 VIL tRAH tCAH tASC tASR ROW ADDRESS ROW ADDRESS COLUMN ADDRESS tCWL tRWL tWP tRCS /W VIH VIL tWCH tDZC DQ (INPUTS) VIH tDS tDH DATA VALID Hi-Z VIL tCLZ DQ (OUTPUTS) VOH Hi-Z Hi-Z VOL tDZO tOEZ tOEH tODD /OE VIH VIL 11 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS tRP VIH /RAS VIL tCRP tCSH tRCD tCRP tRSH tCAS VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH tCAH tASC COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tAWD tCWD tRWD tRCS /W tASR tCWL tRWL tWP VIH VIL tDH tDS tDZC DQ (INPUTS) VIH Hi-Z VIL DATA VALID tCAC tAA tCLZ DQ (OUTPUTS) VOH DATA VALID Hi-Z VOL tRAC Hi-Z tODD tDZO tOEA tOEH tOEZ /OE VIH VIL 12 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tCP tRSH tCAS tASC tCAH tASC VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH ROW ADDRESS tCAH tASC COLUMN-1 COLUMN-2 tCPRH tCAH tASR ROW ADDRESS COLUMN-3 tRCS tRRH tCAL tCAL tCAL tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH Hi-Z tCAC VIL tCAC tAA tCLZ DQ (OUTPUTS) DATA VALID-1 Hi-Z VOL VIL /OE tAA tDOH tDOH VOH tRAC tDZO tCAC tAA tCPA DATA VALID-2 tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEA tOCH tOEZ VIH tODD 13 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tASC tCAH tRSH tCP tCAS tCRP VIH / CAS VIL tCAL tASR VIH A0,B0~A11 VIL tRAH ROW ADDRESS tASC tCAH COLUMN-1 tWCS tWCH COLUMN-2 tWCS tWCH tASC tCAL tCAH COLUMN-3 tWCS tASR ROW ADDRESS tWCH VIH /W VIL tDS DQ (INPUTS) DQ (OUTPUTS) VIH VIL tDH DATA VALID-1 tDS tDH DATA VALID-2 tDS tDH DATA VALID-3 VOH Hi-Z VOL VIL /OE 14 VIH MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read-Write,Read-Modify-Write Cycle tRAS tRP VIH /RAS VIL tCSH tCRP tRCD tRWL tCRP tHPRWC tCAS tCAS tCP VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH tCAH tASC ROW ADDRESS tASC COLUMN-1 tASR ROW ADDRESS COLUMN-2 tAWD tRCS tCWL tCAH tAWD tCWL tCWD tRCS tCWD tWP tWP VIH /W VIL tRWD tDZC DQ (INPUTS) tCPWD VIH tDZC tCLZ tCLZ VOH DATA VALID-1 Hi-Z VOL tRAC tDZO tODD tOEA tCPA tDZO tOEZ 15 DATA VALID-2 Hi-Z VIH /OE DATA VALID-2 Hi-Z tCAC tAA tAA DQ (OUTPUTS) tDH tDS DATA VALID-1 Hi-Z tCAC VIL tDH tDS tOEA Hi-Z tODD tOEH tOEZ VIL MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (1) tRP tRAS /RAS tRWL VIH VIL tCRP tCSH tHPC tCRP tCAS tRCD tHPRWC tCAS tCP tCP tCAS VIH tCWL / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH ROW ADDRESS tASC tCAH tASC tCAL ROW ADDRESS COLUMN-3 tCPWD tAWD tWCH tWCS tASR tASC tCAH COLUMN-2 COLUMN-1 tRCS /W tCAH tCAL tCWD tWP VIH VIL tDZC DQ (INPUTS) VIH tDZ tDS C DATA VALID-2 tCAC VIL tDH tDS DATA VALID-3 tAA tCAC tAA tWEZ tCLZ DQ (OUTPUTS) VOH tCPA tOEA tOEZ VIL tDZO tOEA tOEZ tOEH tOCH VIH tODD 16 DATA VALID-3 VOL tRAC tDZO /OE tCLZ DATA VALID-1 Hi-Z tDH MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC tODD 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (2) VIH /RAS VIL tHPC VIH / CAS VIL tCP tASC A0,B0~A11 tCAS tCAS tCAH tCAH tASC tCAH tASC VIH COLUMN-1 COLUMN-2 COLUMN-3 VIL tCAL tRCH tCAL tWCS tWCH VIH /W tHCWD VIL tHAWD tDH tDS tHPWD DQ (INPUTS) tDZC VIH DATA VALID-2 Hi-Z tCAC VIL tAA tCAC Hi-Z tAA tCPA tWEZ tCPA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 VOL DATA VALID-3 Hi-Z tHCOD tHAOD tDZC tOEZ tOEA tODD VIL /OE 17 tHPOD VIH MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by OE ) tRAS tRP VIH /RAS VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCAS tCP tCRP VIH / CAS VIL tRAD tASR A0,B0~A11 VIH VIL tRAH tCPRH tASC ROW ADDRESS tASC tCAH COLUMN-1 tCAH tASC COLUMN-2 tASR tCAH ROW ADDRESS COLUMN-3 tRAL tRRH tRCS tRCH VIH /W VIL tWEZ tDZC DQ (INPUTS) tRDD tCDD VIH tCAC tCAC VIL tAA tCLZ DQ (OUTPUTS) VOH DATA VALID-1 Hi-Z VOL tRAC tDZO VIL /OE tAA tCAC tAA tDOH tCLZ DATA VALID-1 DATA VALID-2 tOCH Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tCPA tOEZ tOEA tCHOL tOEZ tOEZ tOEA VIH tOEPE 18 Hi-Z MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC tOEPE tODD 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS /RAS tRP VIH VIL tCSH tCRP tCAS tRCD tHPC tCAS tCP tRSH tCAS tCP tCRP VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH ROW ADDRESS tCAH tASC tASC tASC tCAH COLUMN-2 COLUMN-1 tCPRH tCAH tRCH tRCS /W ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRRH tRCH VIH VIL tDZC DQ (INPUTS) tWPE VIH tCAC tCAC VIL tAA tDOH VOH VOL VIL /OE tCAC tAA tWEZ DATA VALID-2 DATA VALID-1 Hi-Z tRAC tDZO Hi-Z tAA tCLZ DQ (OUTPUTS) tRDD tCDD tCPA tOEA tOCH tCLZ Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEZ VIH tODD 19 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM /CAS before /RAS Refresh Cycle tRC tRP /RAS tRC tRAS tRAS tRP VIH VIL tRPC tCSR / CAS tCHR tRPC tCSR tCHR tRPC tCRP VIH VIL tCPN tASR A0,B0~A11 VIH ROW ADDRESS VIL COLUMN ADDRESS tRRH tRCH /W tRCS VIH VIL DQ (INPUTS) DQ (OUTPUTS) VIH VIL tREZ tOHR tOFF tOHC VOH Hi-Z VOL tOEZ VIH /OE VIL 20 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 31) tRC tRAS /RAS tRC tRP tRAS tRP VIH VIL tCRP tRCD tRSH tCHR VIH / CAS VIL tRAD tASR A0,B0~A11 VIH tRAH tASC tASR tCAH COLUMN ADDRESS ROW ADDRESS ROW ADDRESS VIL tRCS /W tRRH tRAL tRCH VIH VIL tCDD tDZC tRDD DQ (INPUTS) VIH Hi-Z VIL tCAC tAA tOFF tOHC tCLZ DQ (OUTPUTS) tREZ tOHR VOH Hi-Z Hi-Z DATA VALID VOL tRAC tDZO tOEA tORH tOEZ tODD VIH /OE VIL Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. 21 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 MITSUBISHI LSIs Preliminary Spec. MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Package outline 133.35±0.13 6.77Max 3±0.13 127.35±0.13 38.1±0.13 17.78±0.13 3±0.13 1±0.13 1.27±0.1 23.495±0.13 MIT - DS - 0218-0.0 43.18±0.13 MITSUBISHI ELECTRIC 13/JUL./1998 5.1Min 5.1Min R2±0.13