MITSUBISHI MH64S72QJA-6

MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH64S72QJA is 64108864 - word x 72-bit
Sy nchronous DRAM stacked structural module. This
consist of thirty -six industry standard 32M x 4
Sy nchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual inline package prov ides any application where high
densities and large of quantities memory are required.
This is a socket-ty pe memory module ,suitable f or
easy interchange or addition of module.
FEATURES
Type name
MH64S72QJA-6
Max.
Frequency
133MHz
CLK
Access Time
[latch mode]
(CL = 4)
1pin
94pin
10pin
95pin
11pin
124pin
40pin
125pin
41pin
168pin
84pin
5.4ns
Utilizes industry standard 32M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst W rite / Single W rite (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
4096 refresh cycles every 64ms
APPLICATION
Main memory unit for computers, Microcomputer memory.
MIT-DS-334-0.0
85pin
MITSUBISHI
ELECTRIC
17/Jun. /1999 1
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NO.
PIN NAME
1
VSS
43
VSS
85
PIN NAME
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
/S2
87
DQ33
129
/S3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
NC
90
VDD
132
NC
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
11
DQ7
DQ8
52
53
CB2
CB3
94
95
DQ39
DQ40
136
137
CB6
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
20
DQ14
DQ15
61
62
NC
NC
103
104
DQ46
DQ47
145
146
NC
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
NC
150
DQ54
NC
151
DQ55
24
NC
66
DQ22
108
25
NC
67
DQ23
109
110
68
VDD
152
VSS
27
VDD
/WE0
VSS
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
/S0
72
DQ27
114
/S1
156
DQ59
31
NC
73
VDD
115
/RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
34
A0
A2
75
76
DQ29
DQ30
117
118
A1
A3
159
160
DQ61
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
BA0
26
38
A10
80
NC
122
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
42
VDD
CK0
83
84
SCL
VDD
125
126
CK1
167
168
SA2
VDD
NC
NC = No Connection
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 2
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add
CKE0
/S0-3
DQM0-7
/W
/RAS
/CAS
REGE
Vdd
RCKE0
R/S0-3
RDQM0-7
DQ0
DQ1
DQ32
DQ33
DQ2
DQ3
DQ4
DQ5
D0
D18
DQ34
DQ35
DQ36
DQ37
D9
D27
DQ6
DQ7
D1
D19
DQ38
DQ39
D10
D28
D11
D29
D12
D30
D13
D31
D14
D32
DQ8
DQ9
DQ10
D2
DQ40
DQ41
DQ42
D20
DQ11
DQ12
DQ43
DQ44
DQ13
DQ14
DQ15
D3
DQ45
DQ46
DQ47
D21
DQ16
DQ48
DQ17
DQ18
DQ19
D4
DQ49
DQ50
DQ51
D22
DQ20
DQ21
DQ52
DQ53
D5
DQ22
DQ23
D23
DQ54
DQ55
DQ24
DQ25
DQ56
DQ57
DQ26
DQ27
DQ28
DQ29
D6
D24
DQ58
DQ59
DQ60
DQ61
D15
D33
DQ30
DQ31
D7
D25
DQ62
DQ63
D16
D34
D17
D35
CB0
CB4
CB1
CB2
D8
CB5
CB6
D26
CB3
CB7
From PLL
CK0
PLL
Terminated
CK1 - CK3
RCKE0
R/S0
R/S1
R/S2
R/S3
D0-35
D0-3,D8-12,D17
D18-21,D26-30,D35
D4-7,D13-16
D22-25,D31-34
MIT-DS-334-0.0
RDQM
RDQM
RDQM
RDQM
RDQM
RDQM
RDQM
RDQM
0
1
2
3
4
5
6
7
SERIAL PD
SCL
D0-1,D18-19
A0 A1 A2
WP
D2-3,D8,D20-21,D26
47K
SA0 SA1 SA2
D4-5,D22-23
D6-7,D24-25
VDD
D9-10,D27-28
D11-12,D17,D29-30,D35
VSS
D13-14,D31-32
D15-16,D33-34
MITSUBISHI
ELECTRIC
SDA
D0 to D35
D0 to D35
17/Jun. /1999 3
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0 - 3
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/W
Input
Combination of /RAS,/CAS,/W defines basic commands.
CK0
A0-11
Input
BA0-1
Input
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
MIT-DS-334-0.0
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
the bank to which a command is applied.BA must be set
with ACT,PRE,READ,WRITE commands
Input/Output Data In and Data out are referenced to the ris ing edge
of CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
Output
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MITSUBISHI
ELECTRIC
17/Jun. /1999 4
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH64S72QJA provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Ref resh Option @ref resh command
A10
Precharge Option @precharge or read/write command
def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burs t read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
term inates burs t read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 5
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
Deselect
DESEL
H
CKE
n
X
No Operation
NOP
H
Row Address Entry &
Bank Activate
ACT
Single Bank Precharge
/CS
/RAS /CAS
/WE
BA0,1
A11
A10
A0-9
H
X
X
X
X
X
X
X
X
L
H
H
H
X
X
X
X
H
X
L
L
H
H
V
V
V
V
PRE
H
X
L
L
H
L
V
X
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
X
X
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
X
L
V
WRITEA
H
X
L
H
L
L
V
X
H
V
READ
H
X
L
H
L
H
V
X
L
V
Column Address Entry
& Read with AutoPrecharge
READA
H
X
L
H
L
H
V
X
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
X
REFSX
L
H
H
X
X
X
X
X
X
X
Self-Refresh Exit
L
H
L
H
H
H
X
X
X
X
Column Address Entry
& Write with AutoPrecharge
Column Address Entry
& Read
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
L
V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 6
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State
/S
IDLE
H
L
X
L
ROW ACTIVE
READ
/RAS /CAS
/WE
Command
Address
X
H
X
H
H
L
BA
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
H
H
DESEL
X
X
Action
NOP
NOP
NOP
TBST
ILLEGAL*2
READ/WRITE ILLEGAL*2
Op-Code,
Bank Active,Latch RA
NOP*4
REFA
Auto-Refresh*5
MRS
Mode Register Set*5
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
L
H
L
H
H
BA,RA
BA,A10
L
L
L
H
L
L
L
L
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
H
L
X
NOP
TBST
NOP(Continue Burst to END)
L
H
L
Mode-Add
READ/READA
WRITE/
Begin Write,Latch CA,
Determine Auto-Precharge
PRE/PREA
Bank Active/ILLEGAL*2
Precharge/Precharge All
REFA
ILLEGAL
MRS
ILLEGAL
Mode-Add
BA
Determine Auto-Precharge
WRITEA
ACT
X
Op-Code,
Begin Read,Latch CA,
Terminate Burst
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3
MIT-DS-334-0.0
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
17/Jun. /1999 7
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
WRITE
H
L
L
/RAS /CAS
X
H
H
X
H
H
/WE
X
H
L
Address
Command
Action
DESEL
NOP(Continue Burst to END)
NOP(Continue Burst to END)
X
X
NOP
TBST
BA
Terminate Burst
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin Read,Determine AutoPrecharge*3
WRITE/
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
H
L
L
H
BA,A10
L
L
L
PRE/PREA
REFA
L
L
L
L
READ with
H
X
X
X
X
AUTO
L
H
H
H
L
H
H
L
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
L
L
H
BA,A10
L
L
L
H
L
L
L
L
Op-Code,
Mode-Add
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
AUTO
L
H
H
H
X
NOP
NOP(Continue Burst to END)
PRECHARGE
L
L
H
L
H
BA
BA,CA,A10
TBST
H
H
L
L
H
L
L
BA,CA,A10
L
L
L
H
L
H
H
L
BA,RA
BA,A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
PRECHARGE
L
WRITE with
MIT-DS-334-0.0
X
Op-Code,
WRITEA
MRS
Mode-Add
Begin Write,Determine AutoPrecharge*3
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
ILLEGAL
DESEL
NOP(Continue Burst to END)
X
NOP
NOP(Continue Burst to END)
BA
TBST
ILLEGAL
X
READ/READA ILLEGAL
WRITE/
ILLEGAL
WRITEA
ACT
Bank Active/ILLEGAL*2
PRE/PREA
REFA
MRS
ILLEGAL*2
ILLEGAL
ILLEGAL
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
ACT
PRE/PREA
MITSUBISHI
ELECTRIC
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
17/Jun. /1999 8
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
PRE -
H
X
X
X
X
DESEL
NOP(Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACTIVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
H
X
X
X
L
H
H
L
WRITE RECOVERING
MIT-DS-334-0.0
/RAS /CAS
/WE
Command
Address
Action
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
ILLEGAL*2
NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
REFA
ILLEGAL
MRS
ILLEGAL
X
DESEL
NOP
H
X
NOP
NOP
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
REFA
ILLEGAL
MRS
ILLEGAL
17/Jun. /1999 9
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Address
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
Action
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Addres s , NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified s tate; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle s tate.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 10
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CK
n-1
CK
n
/S
SELF -
H
X
X
X
REFRESH*1
L
H
H
L
H
L
/RAS /CAS
/WE
Add
Action
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High trans ition will re-enable CK and other inputs asynchronously.
A m inimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 11
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CLK
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register(MRS). The mode
register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC
from a MRS command, the SDRAM is ready for new command.
/CS
/RAS
/CAS
/WE
V
BA0,1 A11-A0
BA0 BA1 A11 A10 A9
0
0
0
CL
LATENCY
MODE
WRITE
MODE
0
WM
A8
0
R
R
2
011
3
100
101
R
R
110
111
R
R
1
0
A5
A4 A3
LTMODE
A1 A0
A2
BT
BL
/CAS LATENCY
000
001
010
0
A7 A6
BURST
SINGLE BIT
BL
000
001
010
BURST
LENGTH
011
100
101
110
111
BURST
TYPE
0
1
BT= 0
1
2
BT= 1
4
8
4
8
R
R
R
R
R
FP
R
R
1
2
SEQUENT IAL
INTERLEAVED
R: Reserved for Future Use
FP: Full Page
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 12
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
/CAS Latency
Q1
Q2
Q3
D0
D1
D3
D2
Burst Length
Burst Length
Burst Type
Initial Address BL
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Interleaved
Sequential
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 13
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ 4.6
V
VO
Output Voltage
with respect to Vss
-0.5 ~ 4.6
V
IO
Output Current
50
mA
Pd
Power Dissipation
39
W
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-45 ~ 100
°C
Ta=25°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Typ.
Unit
Vdd
Supply Voltage
Min.
3.0
3.3
Max.
3.6
V
Vss
Supply Voltage
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
CI(A)
Input Capacitance, address pin
CI(C)
CI(CK)
Input Capacitance, control pin
Input Capacitance, CKE pin
CI(K)
Input Capacitance, CK pin
CI/O
Input Capacitance, I/O pin
MIT-DS-334-0.0
Test Condition
VI = Vss
f=1MHz
Vi=25mVrms
MITSUBISHI
ELECTRIC
Limits(max.)
Unit
25
pF
25
pF
50
pF
50
pF
29
pF
17/Jun. /1999 14
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Parameter
Symbol
Limits
(max)
Test Condition
-6
operating current
one bank activ e (discrete)
precharge stanby current
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
in non power-down mode
one bank activ e (discrete)
burst current
auto-refresh current
self-refresh current
Icc1
tRC=min.tCLK=min, BL=1, I OL =min
2645
Unit
mA
107
Icc2P
CKE=VILmax,tCLK=15ns
Icc2PS CKE=CLK=VILmax(fixed)
Icc2N CKE=/CS=VIHmin,tCLK=15ns(Note)
Icc2NS CKE=VIHmin,CLK=VILmax(f ixed)
Icc3N CKE=/CS=VIHmin,tCLK=15ns
mA
71 mA
935 mA
575 mA
1475 mA
Icc3NS CKE=VIHmin,CLK=VILmax(f ixed)
tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte)
Icc4
1295 mA
Icc5
Icc6
tRC=min, tCLK=min
3815 mA
7235 mA
107 mA
CKE <0.2V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Test Condition
Parameter
VOH(DC) High-Level Output Voltage(DC)
VOL(DC) Low-Level Output Voltage(DC)
Off-stare Output Current
IOZ
Input Current
Ii
MIT-DS-334-0.0
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd
VIH=0 ~ Vdd+0.3V
MITSUBISHI
ELECTRIC
Limits
Unit
Min. Max.
2.4
V
0.4 V
-10
-10
10 uA
10 uA
17/Jun. /1999 15
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Tim ing Measurement Level: 1.4V
LATCH MODE
Limits
-6
Max.
Min.
Symbol Parameter
tCLK
CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle tim e
Row to Column Delay
Row Active tim e
Row Precharge time
Write Recovery tim e
Act to Act Deley tim e
Mode Register Set Cycle time
Self Refresh Exit tim e
Power Down Exit tim e
Refresh Interval tim e
CL=3
CL=4
7.5
2.5
2.5
1
1.5
0.8
67.5
22.5
10
45
22.5
15
100000
15
15
7.5
7.5
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
CK
1.4V
Signal
1.4V
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
Any AC tim ing is
referenced to the input
signal crossing
through 1.4V.
17/Jun. /1999 16
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
-6
Max.
Min.
Symbol Parameter
tCLK
CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle tim e
Row to Column Delay
Row Active tim e
Row Precharge time
Write Recovery tim e
Act to Act Deley tim e
Mode Register Set Cycle time
Self Refresh Exit tim e
Power Down Exit tim e
Refresh Interval tim e
CL=2
CL=3
7.5
10
2.5
2.5
1
6.5
0
67.5
22.5
10
45
22.5
15
100000
15
15
7.5
7.5
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Limits
-8
Min. Max.
Symbol Parameter
tAC
Access time from CK
tOH
Output Hold tim e
from CK
tOLZ
tOHZ
ns
CL=4
2.7
ns
0
ns
CL=4
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
MIT-DS-334-0.0
5.4
CL=3
CL=3
Unit
2.7
MITSUBISHI
ELECTRIC
5.4
ns
17/Jun. /1999 17
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
-6
Min. Max.
Symbol Parameter
tAC
Access time from CK
tOH
Output Hold tim e
from CK
tOLZ
tOHZ
CL=2
5.4
CL=3
6.0
CL=2
2.7
CL=3
3.0
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
ns
ns
ns
0
2.7
Unit
5.4
ns
Output Load Condition
CK
1.4V
DQ
1.4V
VOUT
50pF
Output Timing
Measurement
Ref erence Point
1.4V
CK
DQ
1.4V
tAC
MIT-DS-334-0.0
tOH
tOHZ
MITSUBISHI
ELECTRIC
17/Jun. /1999 18
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
11
10
12
13
14
15
17
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
D0
DQ
ACT#0
D0
WRITE#0
D0
D0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 19
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
1
0
3
2
5
4
7
6
BL=4,Buffer mode(REGE="L")
9
8
11
10
13
12
15
14
17
16
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
D1
D1
0
1
2
Y
0
REGE
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D1
D1
PRE#0
WRITE#1
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 20
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4,Lacth mode(REGE="H")
9
8
11
10
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
D0
DQ
ACT#0
WRITE#0
D0
D0
D0
PRE#0
D0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 21
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
WRITE CYCLE (dual bank)
1
0
3
2
5
4
BL=4,Latch mode(REGE="H")
7
6
9
8
11
10
13
12
15
14
17
16
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
D0
D1
1
2
Y
0
REGE
D0
DQ
ACT#0
WRITE#0
ACT#1
D0
D0
D1
D1
PRE#0
WRITE#1
D1
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 22
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4,CL=3,Buffer mode(REGE="L")
9
8
11
10
12
13
14
15
17
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥ BL allows full data out
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 23
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
1
0
3
2
4
5
BL=4,CL=3,Buffer mode(REGE="L")
7
6
9
8
11
10
13
12
15
14
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
Q1
Q1
Q1
Y
0
REGE
CL=3
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
READ#0
ACT#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 24
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (single bank)
1
0
2
3
5
4
7
6
BL=4, CL=3,Latch mode(REGE="H")
9
8
11
10
12
13
14
15
17
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =3
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ≥ BL allows full data out
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 25
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
READ CYCLE (dual bank)
1
0
3
2
4
5
BL=4,CL=3,Latch mode(REGE="H")
7
6
9
8
11
10
13
12
15
14
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =3
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
Q1
Q1
Q1
Y
0
REGE
CL=3
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
READ#0
ACT#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 26
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
6
5
8
7
BL=4,Buffer mode(REGE="L")
10
9
11
12
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
/CAS
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-9
X
X
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
Y
Y
0
X
Y
X
0
0
1
D1
D0
D0
1
Y
1
REGE
D0
DQ
ACT#0
ACT#1
D0
D0
D0
WRITE#0 with
AutoPrecharge
D1
D1
D1
ACT#0
WRITE#1 with
AutoPrecharge
D0
WRITE#0
ACT#1
D0
D1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 27
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
6
5
8
7
BL=4,Latch mode(REGE="H")
10
9
12
11
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
/CAS
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-9
X
X
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
Y
Y
0
X
1
Y
0
0
X
Y
1
1
REGE
D0
DQ
ACT#0
ACT#1
D0
D0
WRITE#0 with
AutoPrecharge
D0
D1
D1
D1
D1
ACT#0
WRITE#1 with
AutoPrecharge
D0
D0
WRITE#0
ACT#1
D0
D0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 28
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
5
6
8
7
BL=4,Buffer mode(REGE="L")
10
9
12
11
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
A0-9
X
X
Y
Y
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
0
X
1
Y
0
0
X
Y
1
1
REGE
CL=3
CL=3
Q0
DQ
ACT#0
ACT#1
READ#0 with
Auto-Precharge
Q0
Q0
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 29
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
0
1
2
4
3
5
6
8
7
BL=4,Latch mode(REGE="H")
10
9
12
11
14
13
16
15
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =3
A0-9
X
X
Y
Y
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
0
X
1
Y
0
0
X
Y
1
1
REGE
CL=3
CL=3
Q0
DQ
ACT#0
ACT#1
READ#0 with
Auto-Precharge
Q0
Q0
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 30
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
1
0
3
2
5
4
7
6
9
8
BL=4,Buffer mode(REGE="L")
11
10
12
13
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
D0
DQ
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 31
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
1
0
3
2
5
4
7
6
9
8
BL=4,Latch mode(REGE="H")
11
10
12
13
15
14
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
D0
DQ
ACT#0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 32
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
1
0
3
2
4
5
7
6
9
8
BL=4,Buffer mode(REGE="L")
11
10
13
12
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
CL=3
CL=3
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 33
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
1
0
3
2
4
5
7
6
9
8
BL=4,Latch mode(REGE="H")
11
10
13
12
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
CL=3
CL=3
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 34
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0
1
2
4
3
6
5
8
7
BL=4,Buffer mode(REGE="L")
10
9
12
11
13
14
16
15
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
REGE
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
READ#0
WRITE#0 WRITE#0 WRITE#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 35
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
0
1
2
4
3
6
5
8
7
BL=4,Latch mode(REGE="H")
10
9
12
11
13
14
16
15
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
REGE
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
READ#0
WRITE#0 WRITE#0 WRITE#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999 36
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
1
0
3
2
4
5
7
6
BL=4,Buffer mode(REGE="L")
9
8
11
10
12
13
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
DQ
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
REGE
ACT#0
READ#0
WRITE#0
READ#0 READ#0 READ#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
37
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
1
0
3
2
4
5
7
6
BL=4,Latch mode(REGE="H")
9
8
11
10
12
13
14
15
17
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
DQ
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
REGE
ACT#0
READ#0
WRITE#0
READ#0 READ#0 READ#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
38
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0
1
2
4
3
6
5
8
7
BL=4,Buffer mode(REGE="L")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
1
0
D0
DQ
Y
D0
D0
D0
X
1
0
D1
D1
1
1
Y
1
D1
D1
D1
REGE
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
39
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
0
1
2
4
3
6
5
8
7
BL=4,Latch mode(REGE="H")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
Y
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
1
0
D0
DQ
D0
D0
X
1
0
1
D0
D1
D1
1
Y
1
D1
D1
D1
REGE
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
40
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0
2
1
4
3
5
6
8
7
BL=4,Buffer mode(REGE="L")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9
X
X
Y
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
1
0
Q0
DQ
X
1
0
1
Q0
Q0
Q0
1
Q1
Y
1
Q1
REGE
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
41
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
0
2
1
4
3
5
6
8
7
BL=4,Latch mode(REGE="H")
10
9
11
12
13
14
16
15
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-9
X
X
Y
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
1
0
Q0
DQ
X
1
0
1
Q0
Q0
Q0
1
Q1
Y
1
Q1
REGE
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
42
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
1
0
2
3
4
5
6
7
8
9
10
11
12
13
15
14
17
16
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
M
A0-9
X
A10
X
A11
X
0
BA0,1
0
Y
0
D0
DQ
D0
D0
D0
REGE
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
43
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
11
10
13
12
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
0
D0
DQ
D0
D0
D0
REGE
Auto-Refresh
ACT#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
WRITE#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
44
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
CLK can be stopped
tRC
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
DQ
REGE
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
45
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0
2
1
4
3
6
5
BL=4,Buffer mode(REGE="L")
8
7
9
10
12
11
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
DQ
D0
D0
D0
masked
D0
D0
D0
REGE
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
46
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask @BL=4
0
2
1
4
3
6
5
BL=4,Latch mode(REGE="H")
8
7
10
9
12
11
13
14
16
15
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
DQ
D0
D0
D0
masked
D0
D0
D0
REGE
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
47
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0
2
1
4
3
5
6
BL=4,Buffer mode(REGE="L")
8
7
10
9
12
11
13
14
16
15
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
DQ
Q0
Q0
Q0
masked
Q0
Q0
Q0
REGE
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
48
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask @BL=4 CL=3
0
2
1
4
3
5
6
BL=4,Latch mode(REGE="H")
8
7
10
9
12
11
13
14
16
15
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=3
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
DQ
Q0
Q0
Q0
masked
Q0
Q0
Q0
REGE
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
49
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0
1
2
3
4
5
6
8
7
10
9
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
DQ
REGE
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
50
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
1
0
2
3
5
4
BL=4,Buffer mode(REGE="L")
7
6
9
8
11
10
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
0
0
D0
DQ
D0
D0
D0
Q0
Q0
Q0
Q0
REGE
ACT#0
READ#0
WRITE#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
51
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend @BL=4 CL=3
1
0
2
3
5
4
BL=4,Latch mode(REGE="H")
7
6
9
8
11
10
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
0
0
D0
DQ
D0
D0
D0
Q0
Q0
Q0
Q0
REGE
ACT#0
READ#0
WRITE#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
52
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
Function described
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A10
0B
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x72
48
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
7.5ns
75
5.4ns
54
ECC
02
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x4
04
Error Checking SDRAM data width
x4
04
1
01
14
15
Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
1/2/4/8/Full page
8F
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
3
04
19
CS# Latency
0
01
20
Write Latency
0
01
21
SDRAM Module Attributes
buffered,registered
1F
Precharge All,Auto precharge
Write1/Read Burst
0E
N/A
00
N/A
00
22
23
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency)
N/A
00
27
Precharge to Active Minimum
22.5ns
17
28
Row Active to Row Active Min.
15ns
0F
29
RAS to CAS Delay Min
22.5ns
17
30
Active to Precharge Min
45ns
2D
tAC for CL=2
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
53
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31
Density of each bank on module
256MByte
40
Command and Address signal input setup time
1.5ns
15
33
Command and Address signal input hold time
0.8ns
08
34
Data signal input setup time
1.5ns
15
35
Data signal input hold time
0.8ns
08
32
36-61
Superset Information (may be used in future)
option
00
62
SPD Revision
rev 2
02
63
Checksum for bytes 0-62
Check sum
EE
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufactures Part Number
91-92
Revision Code
PCB revision
Manufacturing date
year/week code
yyww
serial number
ssssssss
93-94
MH64S72QJA-6
4D483634533732514A412D36202020202020
rrrr
95-98
Assembly Serial Number
99-125
Manufacture Specific Data
option
00
126
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
CL=3,AP,CK0
8D
128+
Unused storage locations
MIT-DS-334-0.0
open
MITSUBISHI
ELECTRIC
00
17/Jun. /1999
54
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
3
8.89
6.35
11.43
1.27
6.35
36.83
24.495
3
54.61
42.18
127.35
43.18
6.5
Max
MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
55
MITSUBISHI LSIs
MH64S72QJA -6
4,831,838,208-BIT ( 64,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
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Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or ci rcuit application examples contained in
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Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
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Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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5.The prior written approval of Mitsubishi Electric Corporation is necessary to
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the approved destination.
Any diversion or reexport contrary to the export control laws and
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7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
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MIT-DS-334-0.0
MITSUBISHI
ELECTRIC
17/Jun. /1999
56