MITSUBISHI M2V56S30TP

SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20TP is a 4-bank x 16777216-word x 4-bit,
M2V56S30TP is a 4-bank x 8388608-word x 8-bit,
M2V56S40TP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz
(-6), and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
Max. Frequency
@CL2
Max. Frequency
@CL3
Standard
M2V56S20/30/40TP-6
100MHz
133MHz
PC133 (CL3)
M2V56S20/30/40TP-7
100MHz
100MHz
PC100 (CL2)
M2V56S20/30/40TP-8
77MHz
100MHz
PC100 (CL3)
MITSUBISHI ELECTRIC
1
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
PIN CONFIGURATION
(TOP VIEW)
x4
x8
Vdd
Vdd
NC
DQ0
VddQ
VddQ
NC
NC
DQ0
DQ1
VssQ
VssQ
NC
NC
NC
DQ2
VddQ
VddQ
NC
NC
DQ1
DQ3
VssQ
VssQ
NC
NC
Vdd
Vdd
NC
NC
/WE
/WE
/CAS
/CAS
/RAS
/RAS
/CS
/CS
BA0
BA0
BA1
BA1
A10/AP A10/AP
A0
A0
A1
A1
A2
A2
A3
A3
Vdd
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
DQM, DQMU/L
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
x16
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable / Write Mask
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
2
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
BLOCK DIAGRAM
DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
I/O Buffer
Memory
Array
Bank #0
Memory
Array
Bank #2
Memory
Array
Bank #1
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
A0-12
BA0,1
Type Designation Code
M 2 V 56 S 4 0
CLK
CKE
/CS /RAS /CAS /WE DQMU/L
This rule is applied to only Synchronous DRAM family.
TP - 8
Speed Grade 6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2
8: 100MHz@CL3
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2n 2: x4, 3: x8, 4: x16
SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits
Interface V:LVTTL
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11. A10 is also used to indicate precharge option. When A10 is
high at a read / write command, an auto precharge is performed. When
A10 is high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-15
Input / Output
DQM
DQMU/L
Input
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
the current cycle is masked. When DQMU/L is high in burst read, Dout is
disabled at the next but one cycle.
MITSUBISHI ELECTRIC
4
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40TP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (autoprecharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS
/CAS
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
X
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
/WE BA0,1
A10
/AP
A0-9, note
11-12
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
6
1
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State
/CS
/RAS
/CAS
/WE
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
L
L
L
L
X
Op-Code,
Mode-Add
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
ROW ACTIVE
READ
L
H
L
H
Address
BA, CA, A10
Command
Action
READ / WRITE ILLEGAL*2
Bank Active, Latch RA
NOP*4
REFA
Auto-Refresh*5
MRS
Mode Register Set*5
Terminate Burst, Latch CA,
READ / READA Begin New Read, Determine
Auto-Precharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge*3
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
MITSUBISHI ELECTRIC
7
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
WRITE
H
X
X
X
L
H
H
L
H
H
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
Address
Command
Action
X
DESEL
NOP (Continue Burst to END)
H
X
NOP
NOP (Continue Burst to END)
L
X
TBST
Terminate Burst
Terminate Burst, Latch CA,
READ / READA Begin Read, Determine AutoPrecharge*3
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine AutoPrecharge*3
Bank Active / ILLEGAL*2
Terminate Burst, Precharge
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
Bank Active / ILLEGAL*2
ILLEGAL*2
MITSUBISHI ELECTRIC
8
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
PRE CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE / PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
WRITE RECOVERING
Address
Command
Action
READ / WRITE ILLEGAL*2
ILLEGAL*2
NOP*4 (Idle after tRP)
READ / WRITE ILLEGAL*2
READ / WRITE ILLEGAL*2
MITSUBISHI ELECTRIC
9
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS
/CAS
/WE
REFRESHING
H
X
X
X
X
DESEL
NOP (Idle after tRC)
L
H
H
H
X
NOP
NOP (Idle after tRC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP (Idle after tRSC)
L
H
H
H
X
NOP
NOP (Idle after tRSC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MODE
REGISTER
SETTING
Address
Command
Action
READ / WRITE ILLEGAL
READ / WRITE ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
10
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State
SELFREFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
ANY STATE
other than
listed above
CKE
n-1
CKE
n
/CS
H
X
X
X
L
H
H
L
H
L
/RAS /CAS
/WE
Add
Action
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Suspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be
satisfied before any command other than EXIT.
2. Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MITSUBISHI ELECTRIC
11
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
AUTO
REFRESH
REFA
IDLE
CKEL
CLK
SUSPEND
CKEH
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
TBST
WRITE
READ
WRITEA
CKEL
TBST
READA
READ
WRITE
WRITE
SUSPEND CKEH
WRITE
CKEL
READ
CKEH
WRITEA
READA
WRITEA
READA
CKEL
WRITEA
WRITEA
SUSPEND CKEH
POWER
APPLIED
POWER
ON
READ
SUSPEND
PRE
CKEL
PRE
PRE
READA
PRE
CKEH
READA
SUSPEND
PRE
CHARGE
Automatic Sequence
Command Sequence
MITSUBISHI ELECTRIC
12
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CLK
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when all banks are
in idle state. After tRSC from a MRS command, the SDRAM is ready
for new command.
/CS
/RAS
/CAS
/WE
BA0,1 A12-A0
BA0 BA1 A12 A11 A10 A9
0
LATENCY
MODE
0
0
0
CL
000
001
010
011
100
101
110
111
0
SW
SW
0
1
A8
A7
0
0
A6
A5
A4
LTMODE
A3
A2
BT
Burst Write
Single Write
/CAS LATENCY
R
R
2
3
R
R
R
R
A1
V
A0
BL
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BURST
TYPE
0
1
BT=0
1
2
4
8
R
R
R
Full Page
BT=1
1
2
4
8
R
R
R
R
SEQUENTIAL
INTERLEAVED
R: Reserved for Future Use
MITSUBISHI ELECTRIC
13
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
CLK
Command
Read
Write
Y
Y
Address
Q0
DQ
Q1
Q2
Q3
D0
D1
D2
D3
/CAS Latency
CL= 3
BL= 4
Burst Length
Burst Length
Burst Type
Initial Address BL
Column Addressing
A2
A1
A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
-
-
1
2
MITSUBISHI ELECTRIC
14
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
ACT
ACT
tRRD
READ
tRCD
ACT
tRP
A0-9,11-12
Xa
Xb
Yb
A10
Xa
Xb
0
BA0-1
00
01
01
DQ
PRE
Xa
1
Xa
00
Qb0
Qb1
Qb2
Qb3
Precharge All
READ
A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A09 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst
Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The
internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL ≥ tRASmin must be met.
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Multi Bank Interleaving Read (CL=2, BL=4)
CLK
Command
ACT
READ
ACT
READ PRE
tRCD
tRCD
ACT
tRP
A0-9,11-12
Xa
Ya
Xb
Yb
A10
Xa
0
Xb
0
0
Xa
BA0-1
00
00
01
01
00
00
Qa2
Qa3
DQ
Qa0
Qa1
Xa
Qb0
Qb1
Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK
Command
ACT
READ
tRCD
ACT
BL
tRP
A0-9,11-12
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
00
DQ
Qa0
Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK
Command
ACT
READ
tRCD
DQ
CL=2
DQ
CL=3
ACT
BL
Qa0
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qa3
internal precharge starts
MITSUBISHI ELECTRIC
16
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4),
A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length
to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst
Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD.
From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is
high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE,
PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal
precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL +
tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 ≥ tRASmin must be met.
Write (BL=4)
CLK
Command
ACT
Write
PRE
BL
tRCD
A0-9,11-12
Xa
Ya
A10
Xa
0
BA0-1
00
00
ACT
tRP
Xa
0
Xa
00
tWR
DQ
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK
Command
ACT
Write
ACT
tRCD
BL
tRP
A0-9,11-12
Xa
Ya
Xa
A10
Xa
1
Xa
BA0-1
00
00
00
tWR
DQ
Da0
Da1
Da2
Da3
internal precharge starts
MITSUBISHI ELECTRIC
17
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is
allowed. READ to READ interval is minimum 1 CLK.
Read interrupted by Read (CL=2, BL=4)
CLK
Command
READ
READ READ
A0-9,11-12
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
Qa1
Qa2
DQ
Qa0
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed.
In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.
The output is disabled automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command
ACT
READ
Write
A0-9,11-12
Xa
Ya
Ya
A10
Xa
0
0
BA0-1
00
00
00
DQM
DQ
Qa0
Da0
Da1
Output disable by DQM
Da2
Da3
by WRITE
MITSUBISHI ELECTRIC
18
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is
minimum 1 CLK.
A PRE command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Precharge (BL=4)
CLK
Command
READ
DQ
Command
PRE
Q0
READ
Q1
Q2
PRE
CL=2
DQ
Command
Q0
READ PRE
DQ
Command
Q0
READ
PRE
DQ
Command
Q1
READ
Q0
Q1
Q0
Q1
Q2
PRE
CL=3
DQ
Command
DQ
READ PRE
Q0
MITSUBISHI ELECTRIC
19
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and
disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1
CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Terminate (BL=4)
CLK
Command
READ
DQ
Command
TBST
Q0
READ
Q1
Q2
TBST
CL=2
DQ
Command
Q0
READ TBST
DQ
Command
Q0
READ
TBST
DQ
Command
Q1
READ
Q0
Q1
Q0
Q1
Q2
TBST
CL=3
DQ
Command
DQ
READ TBST
Q0
MITSUBISHI ELECTRIC
20
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
Write
Write
Write
A0-9,11-12
Ya
Yb
Yc
A10
0
0
0
BA0-1
00
00
10
DQ
Da0
Db0
Dc0
Da1
Da2
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command
ACT
Write
READ
A0-9,11-12
Xa
Ya
Yb
A10
Xa
0
0
BA0-1
00
00
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
don't care
MITSUBISHI ELECTRIC
21
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by
DQM.
Write interrupted by Precharge (BL=4)
CLK
Command
ACT
Write
PRE
ACT
tRP
A0-9,11-12
Xa
Ya
Xa
A10
0
0
0
0
BA0-1
00
00
00
00
DQM
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is
not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK
Command
ACT
Write
A0-9,11-12
Xa
Ya
Yb
A10
0
0
0
BA0-1
00
00
00
DQ
Da0
TBST
Da1
Write
Db0
Db1
Db2
Db3
MITSUBISHI ELECTRIC
22
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT
comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a
command to the same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
Command
Write
ACT
Write
BL
A0-9,11-12
Ya
tRP
Xa
Yb
tWR
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
auto-precharge
Db0
Db1
Db2
Db3
interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
Write
ACT
Read
BL
A0-9,11-12
Ya
tRP
Xa
Yb
tWR
A10
1
0
Xa
BA0-1
00
10
00
DQ
Da0
Da1
auto-precharge
Qb0
Qb1
Qb2
interrupted
Qb3
activate
MITSUBISHI ELECTRIC
23
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ]
Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can
be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
Read
Read
ACT
BL
A0-9,11-12
tRP
Ya
Yb
Xa
A10
1
0
Xa
BA0-1
00
10
00
DQ
Qa0
auto-precharge
Qa1
interrupted
Qb0
Qb1
Qb2
Qb3
activate
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst read / write is
repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst,
a read / write with auto-precharge command is illegal.
Single Write
When sigle write mode is set, burst length for write is always one, independently of Burst Length
defined by (A2-0).
MITSUBISHI ELECTRIC
24
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an autorefresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any
command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-12
BA0-1
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
25
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh
mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and
ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After
tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
/CS
/RAS
/CAS
/WE
CKE
new command
A0-12
X
BA0-1
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
MITSUBISHI ELECTRIC
26
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By
negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output
suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend
can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CLK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP
Active Power Down
CKE
Command
ACT
NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
DQ
Write
D0
Read
D1
D2
D3
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
DQM CONTROL
DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for
reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0.
During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK
Command
Write
Read
DQMU/L
DQ
D0
D2
D3
masked by DQMU/L=H
Q0
Q1
Q3
disabled by DQMU/L=H
MITSUBISHI ELECTRIC
28
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
1000
mW
Ta = 25 °C
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-65 ~ 150
°C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Vdd
Unit
Min.
Typ.
Max.
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VddQ
Supply Voltage for Output
3.0
3.3
3.6
V
VssQ
Supply Voltage for Output
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
CI(A)
Parameter
Test Condition
Input Capacitance, address pin
CI(C)
Input Capacitance, control pin
CI(K)
Input Capacitance, CLK pin
CI/O
Input Capacitance, I/O pin
VI=1.4v
f=1MHz
VI=25mVrms
Limits
Unit
Min.
Max.
2.5
3.8
pF
2.5
3.8
pF
2.5
3.5
pF
4.0
6.5
pF
MITSUBISHI ELECTRIC
29
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3P
Icc3PS
Icc3N
Icc3NS
Icc4
Parameter
Operating Current
(1bank)
Idle Standby Current
in Power Down Mode
Idle Standby Current
in Normal Mode
Test Conditions
Limits(max)
Organiz
100 Unit Note
ation 133
MHz
MHz
x4
90
80
x8
90
80
x16
100
90
1.5
1
mA
tCLK=∞, CKE≤VILmax
1
1
mA
tCLK=min, CKE≥VIHmin,
/CS≥ VIHmin
25
20
mA
2,3
tCLK=∞, CKE≥VIHmin
6
6
mA
2,4
5
4
mA
4
4
mA
30
25
mA
3,5
15
15
mA
4,5
x4
110
90
x8
110
90
mA
5
x16
120
100
180
170
mA
3
3
mA
tCLK=min, tRC=min, BL=1
tCLK=min, CKE≤VILmax
Active Standby Current tCLK=min, CKE≤VILmax
in Power Down Mode tCLK=∞, CKE≤VILmax
tCLK=min, CKE≥VIHmin,
Active Standby Current /CS≥ VIHmin
in Normal Mode
tCLK=∞, CKE≥VIHmin
Burst Operating
Current
tCLK=min, BL=4, gapless data
Icc5
Auto-Refresh Current
tCLK=min, tRFC=min
Icc6
Self-Refresh Current
CKE≤0.2v
-6/-7/-8
mA
1
2
5
Notes
1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle
2. all banks are idle
3. input signals are changed one time during 3xtCLK
4. input signals are stable
5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Test Conditions
VOH(DC)
High-Level Output Voltage (DC)
IOH=-2mA
VOL(DC)
Low-Level Output Voltage (DC)
IOL= 2mA
IOZ
Off-state Output Current
Q floating Vo=0 ~ VddQ
II
Input Current
VIH=0 ~ VddQ+0.3V, other input pins=0V
Limits
Min.
Max.
2.4
Unit
V
0.4
V
-10
10
µA
-10
10
µA
MITSUBISHI ELECTRIC
30
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
Limits
Symbol
Parameter
-6
Min.
-7
Max.
Min.
Unit Note
-8
Max.
Min.
Max.
CL=2
10
10
13
ns
CL=3
7.5
10
10
ns
CLK High pulse width
2.5
3
3
ns
tCL
CLK Low pulse width
2.5
3
3
ns
tT
Transition time of CLK
1
tIS
Input Setup time (all inputs)
1.5
2
2
ns
tIH
Input Hold time (all inputs)
0.8
1
1
ns
tRC
Row Cycle time
67.5
70
70
ns
tCLK
CLK cycle time
tCH
10
1
10
1
10
ns
tRFC
Refresh Cycle time
75
80
80
ns
tRCD
Row to Column Delay
20
20
20
ns
tRAS
Row Active time
45
tRP
Row Precharge time
20
20
20
ns
tWR
Write Recovery time
15
20
20
ns
tRRD
ACT to ACT Delay time
15
20
20
ns
tRSC
Mode Register Set Cycle time
15
20
20
ns
tREF
Average Refresh Interval
CLK
Signal
120000
50
120000
7.8
7.8
50
120000
7.8
ns
µs
1.4V
1.4V
AC timing is referenced to the
input signal crossing through 1.4V.
MITSUBISHI ELECTRIC
31
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits
Symbol
Parameter
-6
Min.
tAC
tOH
-7
Max
Min.
Unit
-8
Max
Min.
Max
CL=2
6
6
7
ns
CL=3
5.4
6
6
ns
Access Time from CLK
CL=2
3
3
3
ns
CL=3
3
3
3
ns
0
0
ns
Output Hold Time from CLK
tOLZ
Delay Time, Output Low
impedance from CLK
0
tOHZ
Delay Time, Output High
impedannce from CLK
3
6
3
6
3
6
ns
Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.
Output Load Condition
Vout
50pF
CLK
1.4V
DQ
1.4V
tOLZ
tAC
tOHZ
tOH
MITSUBISHI ELECTRIC
32
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Burst Write (Single Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
/RAS
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
A12
X
X
BA0,1
0
DQ
Y
0
D0
ACT#0
X
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
0
D0
WRITE#0
D0
D0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
33
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Burst Write (Multi Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRAS
tRP
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
X
A12
X
X
X
X
BA0,1
0
DQ
Y
X
0
1
D0
D0
Y
D0
ACT#0 WRITE#0
ACT#1
D0
X
1
0
D1
D1
PRE#0
D1
Y
0
0
D1
D0
ACT#0
WRITEA#1
(Auto-Precharge)
X
1
D0
D0
0
D0
WRITE#0
PRE#0
ACT#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
34
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Burst Read (Single Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
X
A12
X
X
BA0,1
0
Y
X
0
DQ
0
Q0
ACT#0
READ#0
Q0
Q0
PRE#0
Y
0
0
Q0
0
Q0
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
35
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Burst Read (Multi Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRRD
tRAS
/RAS
tRCD
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
X
A12
X
X
X
X
BA0,1
0
Y
X
0
Y
1
DQ
X
1
Q0
Q0
Q0
0
Q0
ACT#0 READA#0
ACT#1
Y
X
0
Q1
Q1
ACT#0
Q1
1
Q1
Q0
READ#0
0
Q0
Q0
Q0
PRE#0
ACT#1
READA#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
36
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Write Interrupted by Write [BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
A12
X
X
X
BA0,1
0
DQ
Y
X
0
1
D0
D0
ACT#0 WRITE#0
ACT#1
Y
Y
0
D0
D0
Y
1
D0
D1
X
0
D1
D1
WRITE#0 WRITEA#1
interrupt
interrupt
same bank other bank
D0
0
D0
WRITE#0
interrupt
other bank
D0
1
D0
PRE#0
ACT#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
37
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Read Interrupted by Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
A12
X
X
X
BA0,1
0
Y
0
X
Y
1
DQ
1
Q0
ACT#0 READ#0
ACT#1
Y
Q0
Y
1
Q0
Q1
X
0
Q1
Q1
READ#1 READA#1
interrupt
interrupt
other bank same bank
Q1
1
Q1
READ#0
interrupt
other bank
Q0
Q0
Q0
Q0
ACT#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
38
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
X
A10
X
X
A12
X
X
BA0,1
0
1
DQ
Y
Y
Y
0
1
1
D0
ACT#0
D0
WRITE#0
Q1
READ#1
Q1
D1
1
D1
WRITE#1
D1
D1
PRE#1
ACT#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
39
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Write / Read Terminated by Precharge [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
X
X
A12
X
X
X
BA0,1
0
DQ
Y
0
D0
ACT#0
X
0
0
Y
0
D0
WRITE#0
X
0
Q0
PRE#0 ACT#0
Terminate
READ#0
0
Q0
PRE#0
Terminate
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
Y
Y
0
0
0
D0
ACT#0
D0
Q0
WRITE#0 TBST
Q0
READ#0 TBST
D0
0
D0
WRITE#0
D0
D0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Single Write Burst Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
Y
0
0
D0
ACT#0 WRITE#0
Q0
Q0
Q0
Q0
READ#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
42
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Power-Up Sequence and Intialize
CLK
200µs
/CS
tRP
tRFC
tRFC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
MA
X
A10
0
X
A12
0
X
BA0,1
0
0
DQ
NOP
Power On
PRE ALL
REFA
REFA
REFA
MRS
ACT#0
Minimum 8 REFA cycles
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
0
D0
PRE ALL
REFA
ACT#0
D0
D0
D0
WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
44
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Self Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
PRE ALL Self Refresh Entry
Self Refresh Exit
ACT#0
All banks must be idle before REFS is issued.
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
45
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
CLK Suspension [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
Y
Y
0
0
D0
D0
D0
ACT#0 WRITE#0 internal CLK
suspended
D0
Q0
READ#0
Q0
Q0
Q0
internal CLK
suspended
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
46
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
PRE ALL
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
47
MITSUBISHI LSIs
SDRAM (Rev.1.1)
Single Data Rate
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Revison History
Rev.
Date
Description
1.0
July / '99
1.1
Feb. / '00 - Remove "Power-Down" from Function Truth Table for CKE Note 2
- Modify Average Supply Current from Vdd
Icc2N, Icc3N Test Condition (/CS≥ VIHmin)
Icc3PS Limits (from 3mA to 4mA)
Icc5 Limits (from 160/150mA to 180/170mA)
Icc6 Test Condition (CKE ≤0.2V)
Icc6 Limits (from 2mA to 3mA)
- Change Switching Characteristics tAC of -8 for CL=2 from 6ns to 7ns
- Add Note to Switching Characteristics
- Change Output Load Condition to 50pF only
- Remove tCCD from AC Timing Requirements
1st edition
MITSUBISHI ELECTRIC
48
SDRAM (Rev.1.1)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
Feb.2000
256M Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration
to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
2. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any thirdparty’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit
application examples contained in these materials.
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change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
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The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric
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system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi
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8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
49