MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH8S72BCFD is 8388608 - word x 72-bit Synchronous
DRAM module. This consist of eighteen industry standard
8M x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities memory
are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
85pin
1pin
94pin
10pin
95pin
11pin
124pin
40pin
125pin
41pin
168pin
84pin
FEATURES
Type name
MH8S72BCFD-6
Max.
Frequency
133MHz
Access Time from CLK
[component level]
5.4ns
(CL = 4 at Latch mode)
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP
package , industry standard Resistered buffer in TSSOP
package,industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification.
APPLICATION
Main memory or graphic memory in computer systems
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
1
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO.
PIN NAME
PIN NO.
PIN NAME
1
VSS
43
VSS
2
DQ0
44
NC
3
DQ1
45
/S2
4
DQ2
46
5
DQ3
47
6
VDD
7
8
PIN NO.
PIN NAME
PIN NO.
PIN NAME
85
VSS
127
VSS
86
DQ32
128
CKE0
87
DQ33
129
NC
DQMB2
88
DQ34
130
DQMB6
DQMB3
89
DQ35
131
DQMB7
48
NC
90
VDD
132
NC
DQ4
49
VDD
91
DQ36
133
VDD
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
NC
19
DQ14
61
NC
103
DQ46
145
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
CKE1
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
DQ55
25
NC
67
DQ23
109
NC
151
26
VDD
68
VSS
110
VDD
152
VSS
27
/WE
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
/S0
72
DQ27
114
NC
156
DQ59
31
NC
73
VDD
115
/RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
42
VDD
CK0
83
84
SCL
VDD
125
126
CK1
167
168
SA2
VDD
NC
NC = No Connection
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
2
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Add
CKE0
/S0,2
DQM0-7
/W
/RAS
/CAS
RCKE0
R/S0,2
RDQM0-7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
10K
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
D0
DQ6
DQ7
VDD REGE
DQ38
DQ39
DQ40
DQ41
DQ42
DQ8
DQ9
DQ10
DQ11
DQ12
DQ43
DQ44
D1
DQ13
DQ14
DQ15
CB0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
D2
CB4
CB5
CB6
D7
DQ54
DQ55
DQ56
DQ57
CB7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
D6
DQ45
DQ46
DQ47
CB1
CB2
CB3
D5
DQ58
DQ59
D3
D8
DQ60
DQ61
DQ22
DQ23
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
D4
DQ28
DQ29
DQ30
DQ31
From PLL
CK0
CK1 - CK3
RCKE0
R/S0
R/S2
PLL
Terminated
D0-8
D0-2,5-6
D3-4,7-8
MIT-DS-0312-0.0
RDQM 0
RDQM 1
RDQM 2
RDQM 3
RDQM 4
RDQM 5
RDQM 6
RDQM 7
D0
D1-2
D3
D4
D5
D6
D7
D8
MITSUBISHI
ELECTRIC
SERIAL PD
SCL
WP
47K
A0
A1
SDA
A2
SA0 SA1 SA2
VDD
D0 to D8
VSS
D0 to D8
9/May. /1999
3
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0,2
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/W
Input
A0-11
Input
BA0-1
Input
CK0
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
MIT-DS-0312-0.0
Combination of /RAS,/CAS,/W defines basic
commands.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is specifies the four bank to which
a command is applied.BA must be set with ACT ,PRE
,READ ,WRITE commands
Data In and Data out are referenced to the rising edge
Input/Output of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
Input
in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted
Power Supply
module.
Input
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MITSUBISHI
ELECTRIC
9/May. /1999
4
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH8S72BCFD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
Chip Select : L=select, H=deselect
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
5
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
No Operation
DESEL
NOP
Row Adress Entry &
Bank Activate
CKE CKE
n-1
n
H
X
H
X
/S
/RAS /CAS
/WE BA0,1
A11
A10
A0-9
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
PREA
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
H
X
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
X
L
V
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
X
L
H
L
L
V
X
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
X
L
V
Column Address Entry
& Read with Auto
Precharge
READA
H
X
L
H
L
H
V
X
H
V
Auto-Refresh
Self-Refresh Entry
REFA
REFS
Self-Refresh Exit
REFSX
H
H
L
L
H
L
H
H
L
L
H
L
L
L
X
H
L
L
X
H
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Burst Terminate
Mode Register Set
TBST
MRS
H
H
X
X
L
L
H
L
H
L
L
L
X
L
X
L
X
L
X
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
6
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State
/S
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
H
X
X
X
X
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
Bank Active/ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
ROW ACTIVE
READ
/RAS /CAS
/WE
Address
Command
Action
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
Auto-Refresh*5
MRS
Mode Register Set*5
READ/READA
WRITE/
WRITEA
Mode-Add
NOP*4
REFA
DESEL
Op-Code,
Bank Active,Latch RA
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10
WRITE/WRITEA Begin Write,Determine Auto-
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
Precharge*3
MIT-DS-0312-0.0
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
9/May. /1999
7
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS
/CAS
/WE
WRITE
H
X
X
X
X
Address
Command
Action
DESEL
NOP(Continue Burst to END)
L
H
H
H
L
H
H
L
X
NOP
NOP(Continue Burst to END)
BA
TBST
Terminate Burst
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin Read,Determine AutoPrecharge*3
WRITE/
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
Op-Code,
L
L
L
L
READ with
H
X
X
X
Mode-Add
X
AUTO
L
H
H
H
X
PRECHARGE
L
H
H
L
BA
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
WRITEA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
WRITE with
H
X
X
X
X
AUTO
L
L
H
H
H
H
H
L
X
BA
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
PRECHARGE
H
H
H
L
BA,RA
BA,A10
L
L
L
H
X
MIT-DS-0312-0.0
L
L
L
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
DESEL
NOP(Continue Burst to END)
NOP
NOP(Continue Burst to END)
TBST
ILLEGAL
WRITE/
Mode-Add
L
L
Precharge*3
Bank Active/ILLEGAL*2
READ/READA ILLEGAL
Op-Code,
L
L
L
WRITEA
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
DESEL
NOP(Continue Burst to END)
NOP
TBST
NOP(Continue Burst to END)
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
ACT
PRE/PREA
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
9/May. /1999
8
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
PRE -
H
/RAS /CAS
X
X
/WE
X
X
Address
Command
DESEL
NOP(Idle after tRP)
Action
CHARGING
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACTIVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
ILLEGAL*2
NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
Op-Code,
Mode-Add
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRITE ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
Op-Code,
MIT-DS-0312-0.0
Mode-Add
MITSUBISHI
ELECTRIC
9/May. /1999
9
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
Address
Command
Action
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
READ/WRITE ILLEGAL
Op-Code,
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
10
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CKE CKE
n-1
n
/S
/RAS
/CAS
/WE
Add
Action
SELF -
H
X
X
X
X
X
X
INVALID
REFRESH*1
L
H
H
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
11
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
BA0 BA1 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/RAS
/CAS
0
0
0
0
WM
0
0
LTMODE
BT
BL
/WE
BA0,1 A11-0
LATENCY
MODE
WRITE
MODE
CL
/CAS LATENCY
000
001
R
R
010
011
100
101
110
111
2
3
R
R
R
R
0
1
MIT-DS-0312-0.0
BURST
SINGLE BIT
BURST
LENGTH
BURST
TYPE
V
BL
BT= 0
BT= 1
000
001
010
011
1
2
4
8
1
2
4
8
100
101
R
R
R
R
110
111
R
FP
R
R
0
1
SEQUENTIAL
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
MITSUBISHI
ELECTRIC
9/May. /1999
12
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
Initial Address
/CAS
Latency
Q1
Q2
Burst
Length
BL
Q3
D0
Burst Type
D1
D2
D3
Burst
Length
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
13
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ 4.6
V
VO
Output Voltage
with respect to Vss
-0.5 ~ 4.6
V
IO
Output Current
50
mA
Pd
Power Dissipation
13
W
Topr
Operating Temperature
0 ~ 70
C
Tstg
Storage Temperature
-45 ~ 100
C
Ta=25C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted)
Limits
Symbol
Parameter
Vdd
Vss
VIH*1
Min.
Typ.
Max.
Unit
Supply Voltage
3.0
3.3
3.6
V
Supply Voltage
0
0
0
V
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
0.8
V
-0.3
VIL*2
Low-Level Input Voltage all inputs
NOTES)
1. VIH(max)= Vdd-2.0V AC for pulse width less than 3ns acceptable.
2. VIL('min)= -2.0V AC for pulse width less than 3ns acceotable.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
Parameter
Test Condition
Input Capacitance, address pin
CI(C)
Input Capacitance, control pin
CI(K)
Input Capacitance, CK0 pin
CI/O
Input Capacitance, I/O pin
MIT-DS-0312-0.0
1MHz,
1.4V bias
200mV swing
MITSUBISHI
ELECTRIC
Limits(max.)
Unit
20
pF
20
pF
20
pF
16.5
pF
9/May. /1999
14
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
operating current
single bank operation (discrete)
Limits
(max)
Test Condition
1114
Unit Note
mA *1
Icc1
tRC=min.tCLK=min, BL=1, CL=3,IOL=0mA
precharge stanby current in
Non power-down mode
Icc2N
CKE=VIHmin,tCLK=15ns
259
mA *1,2
Icc2NS CLK=VILmax,CKE=VIHmin (fixed)
214
mA *1
precharge stanby current
in Power-down mode
Icc2P
active stanby current
in Non Power Down Mode
Icc3N
active stanby current
in Power Down Mode
Icc3P
CKE=VILmax,tCLK=15ns
70
mA *1,2
Icc2PS CKE=CLK=VILmax(fixed)
43
mA *1
CKE=/CS=VIHmin,tCLK=15ns
Icc3NS CKE=/CS=VIHmin,CLK=VILmax(fixed)
529
mA *1,2
394
mA *1
CKE=VILmax,tCLK=15ns
70
mA *1,2
Icc3PS CKE=CLK=VILmax(fixed)
burst current
Icc4
tCLK=min, BL=4, CL=3, IOL=0mA
all banks active(discerte)
auto-refresh current
Icc5
tRFC=min, tCLK=min
self-refresh current
Icc6
CKE <0.2V
43
mA *1
1339
mA *1
1384
mA *1
43
mA *1
Note)
1.Icc(max) is specified at the output open condition.
2.Input signal are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
Parameter
VOH(DC) High-Level Output Voltage(DC)
VOL(DC) Low-Level Output Voltage(DC)
IOZ
Off-stare Output Current
Ii
Input Current
MIT-DS-0312-0.0
Test Condition
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd
VIH=0 ~ Vdd+0.3V
MITSUBISHI
ELECTRIC
Min. Max.
2.4
0.4
-10 10
-10 10
Unit
V
V
uA
uA
9/May. /1999
15
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Limits
Symbol Parameter
tCLK
CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK High pulse width
CK Low pulse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row Cycle time
Row Refresh Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
Min.
CL=3
CL=4
7.5
2.5
2.5
1
10
1.5
0.8
67.5
80
22.5
45
22.5
15
15
15
7.5
7.5
100K
64
CK
1.4V
Signal
1.4V
MIT-DS-0312-0.0
Max.
MITSUBISHI
ELECTRIC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
9/May. /1999
16
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
Symbol Parameter
tCLK
CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK High pulse width
CK Low pulse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row Cycle time
Row Refresh Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
Min.
CL=2
CL=3
Max.
7.5
2.5
2.5
1
10
6.5
0
67.5
80
22.5
45
22.5
15
15
15
7.5
7.5
100K
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Symbol
Limits
Parameter
tAC
Access time from CK
tOH
Output Hold time from CK
tOLZ
tOHZ
Min.
Max.
CL=3
5.4
CL=4
-
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
Unit
ns
2.7
ns
0
ns
2.7
5.4
Note
*1
ns
NOTE)
1.If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
17
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Limits
Symbol Parameter
Min.
tAC
Access time from CK
tOH
Output Hold time from CK
tOLZ
tOHZ
Unit
CL=2
5.4
CL=3
-
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
ns
2.7
ns
0
ns
2.7
Note
Max.
5.4
*1
ns
NOTE)
1.If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
Output Load Condition
CK
1.4V
DQ
1.4V
VOUT
Ext.CL=50pF
Output Timing
Measurement
Reference Point
CK
1.4V
DQ
1.4V
tAC
MIT-DS-0312-0.0
tOH
tOHZ
MITSUBISHI
ELECTRIC
9/May. /1999
18
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
DQ
D0
ACT#0
D0
WRITE#0
D0
D0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
19
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-9
X
X
A10
X
A11
BA0,1
X
X
X
X
X
X
X
X
X
0
1
Y
Y
0
1
0
D1
D1
0
1
2
Y
0
REGE
DQ
D0
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D1
PRE#0
WRITE#1
D1
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
20
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (single bank)
BL=4,Lacth mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
DQ
D0
ACT#0
WRITE#0
D0
D0
D0
PRE#0
D0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
21
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank)
BL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
D0
D1
0
1
2
Y
0
REGE
DQ
D0
ACT#0
WRITE#0
ACT#1
D0
D0
D1
D1
PRE#0
WRITE#1
D1
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
22
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4,CL=3,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
CL=3
DQ
Q0
ACT#0
READ#0
Q0
Q0
PRE#0
Q0
Q0
ACT#0
Q0
READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
23
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=3,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
Q1
Q1
Q1
Y
0
REGE
CL=3
DQ
CL=3
Q0
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
PRE#0
READ#1
Q1
ACT#0
PRE#1
Q0
READ#0
ACT#2
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
24
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (single bank)
BL=4, CL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =3
A0-9
X
A10
X
X
A11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
REGE
CL=4
DQ
Q0
ACT#0
READ#0
Q0
PRE#0
Q0
Q0
ACT#0
Q0
READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
25
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank)
BL=4,CL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =3
A0-9
X
X
A10
X
A11
BA0,1
Y
Y
X
X
X
X
X
X
X
X
X
0
1
0
1
0
Y
0
1
2
0
Q1
Q1
Q1
Q1
REGE
CL=4
DQ
CL=4
Q0
ACT#0
READ#0
ACT#1
Q0
Q0
PRE#0
READ#1
Q0
ACT#0
PRE#1
READ#0
ACT#2
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
26
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-9
X
X
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
Y
Y
0
X
1
Y
X
0
0
1
D1
D0
D0
Y
1
REGE
DQ
D0
ACT#0
ACT#1
D0
D0
WRITE#0 with
AutoPrecharge
D0
D1
D1
D1
ACT#0
WRITE#1 with
AutoPrecharge
D0
D0
D1
WRITE#0
ACT#1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
27
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst WRITE (multi bank) with AUTO-PRECHARGE
BL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-9
X
X
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
Y
Y
0
Y
X
0
1
0
X
Y
1
1
REGE
DQ
D0
ACT#0
ACT#1
D0
WRITE#0 with
AutoPrecharge
D0
D0
D1
D1
D1
ACT#0
WRITE#1 with
AutoPrecharge
D1
D0
D0
D0
D0
WRITE#0
ACT#1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
28
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=3 Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
A0-9
X
X
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
Y
Y
0
X
1
Y
0
0
X
Y
1
1
REGE
CL=3
CL=3
Q0
DQ
ACT#0
ACT#1
READ#0 with
Auto-Precharge
Q0
Q0
Q0
CL=3
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
29
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Burst READ (multi bank) with AUTO-PRECHARGE
BL=4,CL=4 Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =3
A0-9
X
X
A10
X
X
X
X
A11
X
X
X
X
BA0,1
0
1
Y
Y
0
X
1
Y
0
0
X
Y
1
1
REGE
CL=4
DQ
CL=4
Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
Q0
Q0
CL=4
Q0
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q1
Q1
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
30
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
DQ
D0
ACT#0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D1
D1
WRITE#0
D1
D1
D0
D0
D0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
31
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Write (multi bank)
BL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
DQ
D0
ACT#0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D0
D0
D1
WRITE#0
D1
D1
D1
D0
D0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
32
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=3 Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
CL=3
DQ
CL=3
Q0
ACT#0
READ#0
ACT#1
Q0
Q0
Q0
CL=3
Q0
Q0
Q0
READ#0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
33
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Page Mode Burst Read (multi bank)
BL=4,CL=4 Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
REGE
CL=4
CL=4
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
CL=4
Q0
Q0
Q0
READ#0
Q0
Q0
Q1
Q1
Q1
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
34
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
REGE
CL=3
DQ
D0
ACT#0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
35
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Write / Read
BL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
0
0
0
1
0
REGE
CL=4
DQ
D0
ACT#0
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
36
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=3 Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
DQ
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
REGE
ACT#0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
37
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Read / Write
BL=4,CL=4 Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-9
X
X
A10
X
X
A11
X
X
BA0,1
0
1
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
DQ
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
REGE
ACT#0
READ#0 READ#0 READ#0
READ#0
WRITE#0
blank to prevent bus contention
ACT#1
READ#1
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
38
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
X
A11
X
X
X
BA0,1
0
1
DQ
Y
Y
0
D0
D0
D0
D0
X
1
0
D1
D1
1
1
Y
1
D1
D1
D1
REGE
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
39
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Write Interrupted by Precharge
BL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
X
A10
X
X
X
A11
X
X
X
BA0,1
0
1
DQ
Y
Y
0
D0
D0
D0
X
1
0
1
D0
D1
D1
1
Y
1
D1
D1
REGE
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
40
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=3 Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-9
X
X
Y
Y
A10
X
X
X
A11
X
X
X
BA0,1
0
1
0
Q0
DQ
X
1
0
1
Q0
Q0
Q0
1
Q1
Y
1
Q1
REGE
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
41
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Read Interrupted by Precharge
BL=4,CL=4 Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=3
A0-9
X
X
A10
X
X
X
A11
X
X
X
BA0,1
0
1
Y
0
DQ
Y
X
1
0
1
Q0
Q0
Q0
1
Q0
Q1
Y
1
Q1
REGE
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
42
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
M
X
A10
X
A11
X
BA0,1
0
DQ
0
Y
0
D0
D0
D0
D0
REGE
Auto-Ref (last of 8 cycles)
MIT-DS-0312-0.0
Mode
ACT#0
WRITE#0
Register
Setting
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
9/May. /1999
43
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
0
DQ
D0
D0
D0
D0
REGE
Auto-Refresh
ACT#0
WRITE#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
44
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
CLK can be stopped
tRC+1
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
DQ
REGE
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
45
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask
BL=4,Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
DQ
D0
D0
D0
D0
masked
D0
D0
D0
REGE
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
46
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Write Mask
BL=4,Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
DQ
D0
D0
D0
D0
masked
D0
D0
D0
REGE
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
47
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4, CL=3 Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
DQ
Q0
Q0
Q0
Q0
masked
Q0
Q0
Q0
REGE
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
48
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DQM Read Mask
BL=4,CL=4 Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=3
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
DQ
Q0
Q0
Q0
masked
Q0
Q0
REGE
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
49
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
CKE
Active Power Down
CKE latency=1
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
DQ
REGE
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
50
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend
BL=4,CL=3 Buffer mode(REGE="L")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
DQ
Y
Y
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
REGE
ACT#0
WRITE#0
READ#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
51
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK Suspend
BL=4,CL=4 Latch mode(REGE="H")
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=2
CKE latency=2
DQM
A0-9
X
A10
X
A11
X
BA0,1
0
DQ
Y
Y
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
REGE
ACT#0
WRITE#0
READ#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
52
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table I
Byte
SPD enrty data
SPD DATA(hex)
0
# of Serial PD Bytes Written during Production
128
80
1
Total # of Bytes in SPD device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A8
09
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x72
48
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
7.5ns
75
5.4ns
54
9
Function described
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
SDRAM Access from Clock
tAC for CL=3
11
DIMM Configuration type (Non-parity,Parity,ECC)
ECC
02
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x8
08
14
Error Checking SDRAM data width
x8
08
01
8F
Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
1
1/2/4/8/Full page
17
# Banks on Each SDRAM device
CAS# Latency
4bank
3
04
04
19
CS# Latency
0
01
20
Write Latency
0
01
21
SDRAM Module Attributes
buffered,registered with PLL
1F
22
SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
15
18
Precharge All,Auto precharge
Write1/Read Burst
0E
N/A
00
tAC for CL=2
N/A
00
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
26
27
SDRAM Access form Clock(3rd highest CAS latency)
N/A
23ns(22.5ns)
00
17
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
Precharge to Active Minimum
28
Row Active to Row Active Min.
15ns
0F
29
RAS to CAS Delay Min
23ns(22.5ns)
17
30
Active to Precharge Min
45ns
2D
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
53
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Serial Presence Detect Table II
31
Density of each bank on module
64MByte
10
32
Command and Address signal input setup time
1.5ns
15
33
Command and Address signal input hold time
0.8ns
08
34
Data signal input setup time
1.5ns
15
35
Data signal input hold time
0.8ns
08
36-61
62
Superset Information (may be used in future)
SPD Revision
option
JEDEC2
00
02
63
Checksum for bytes 0-62
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
C3
Germany
04
4D4838533732424346442D36202020202020
73-90
91-92
Manufactures Part Number
Revision Code
MH8S72BCFD-6
PCB revision
93-94
Manufacturing date
year/week code
yyww
rrrr
95-98
Assembly Serial Number
serial number
ssssssss
99-125
126
Manufacture Specific Data
Intetl specification frequency
option
00
64
127
Intel specification CAS# Latency support
CL=3,AP,CK0
8D
128+
Unused storage locations
open
00
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
54
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
133.35
3
8.89
6.35
11.43
1.27
6.35
36.83
24.495
3
54.61
42.18
127.35
38.10
4.0Max
1.27
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
55
MITSUBISHI LSIs
MH8S72BCFD-6
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable,but there is always the possibility that trouble may occur with them.
Trouble with semiconductors consideration to safety when making your circuit designs,with
appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any thirdparty's rights,originating in the use of any product data,diagrams,charts or circuit application examples
contained in these materials.
3.All information contained in these materials,including product data, diagrams and charts,represent
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Electric Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubish
Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering
the use of a product contained herein for special applications,such as apparatus or systems for
transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or
in part these materials.
6.If these products or technologies are subject the Japanese export control restrictions,they must be
exported under a license from the Japanese government and cannot be imported into a country other than
the approved destination. Any diversion or reexport contrary to the export control laws and regulations of
Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
for further details on these materials or the products contained therein.
MIT-DS-0312-0.0
MITSUBISHI
ELECTRIC
9/May. /1999
56