W27C01 128K × 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C01 is a high speed, low power consumption Electrically Erasable and Programmable Read Only Memory organized as 131,072 x 8 bits. It requires only one supply in the range of 5.0V ±5% in normal read mode. The W27C01 provides an electrical chip erase function. FEATURES • • Single power supply voltage: 5.0V ±5% • High speed access time: 70 nS (max.) • Read operating current: 30 mA (max.) • Erase/Programming operating current: 30 mA (max.) • +12V erase/programming voltage Fully static operation • All inputs and outputs directly TTL/CMOS compatible • Three-state outputs • Available packages: 32-pin 600 mil DIP, 32-lead PLCC and 32-lead STSOP • Standby current: 20 µA (max.) PIN CONFIGURATIONS BLOCK DIAGRAM VDD Vss VPP Vpp 1 32 V DD A16 2 31 #PGM A15 3 30 NC A12 4 29 A14 A7 5 28 A13 27 A8 26 25 A9 A11 9 24 #OE 10 23 A10 A1 11 22 A6 6 A5 7 A4 8 A3 A2 32-pin PDIP A0 12 21 #CE Q7 Q0 13 20 Q6 Q1 14 19 Q5 Q2 15 18 Q4 Vss 16 17 Q3 A7 A6 A5 A4 A3 A2 A1 A0 Q0 A A A 1 1 1 2 5 6 V p p # V P D G N D M C 4 3 2 1 3 2 5 6 7 8 9 10 11 12 1 13 4 3 1 32-lead PLCC 1 5 1 6 1 1 7 8 1 9 #PGM #CE CONTROL #OE 3 0 29 28 27 26 25 24 23 2 22 0 21 A14 A13 A8 A9 A11 #OE A10 #CE Q7 A0 . DECODER . OUTPUT BUFFER Q0 . . Q7 CORE ARRAY A16 Q Q V Q Q Q Q 1 2 s 3 4 5 6 s PIN DESCRIPTION A11 A9 A8 A13 A14 NC #PGM V DD V PP A16 A15 A12 A7 A6 A5 A4 1 2 32 31 30 3 4 5 29 28 27 6 7 8 32-lead STSOP 26 25 9 10 24 23 11 12 22 13 14 15 16 21 20 19 18 17 SYMBOL #OE A10 #CE Q7 Q6 Q5 Q4 Q3 V SS Q2 Q1 Q0 A0 A1 A2 A3 A0 − A16 Q0 − Q7 #CE #OE #PGM VPP VDD Vss NC -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable Program/Erase Supply Voltage Power Supply Ground No Connection Publication Release Date: April 15, 2002 Revision A2 W27C01 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C01 has two control functions and both of these produce data at the outputs. #CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from #CE to output (TCE), and data are available at the outputs TOE after the falling edge of #OE, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C01 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (12V), VDD = VCE (5V), #CE low, #OE high, A9 = VHH (12V), A0 low, and all other address pins low and data input pins high. Pulsing #PGM low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VDD = VPE (5V), #CE low, and #OE low, #PGM high. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VDD = VCP (5V), #CE low, #OE high, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing #PGM low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), #CE low, #OE low, and #PGM high. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When #CE high , erasing or programming of non-target chips is inhibited, so that except for the #CE, the W27C01 may have common inputs. Standby Mode The standby mode significantly reduces VDD current. This mode is entered when #CE high. In standby mode, all outputs are in a high impedance state, independent of #OE and #PGM. -2- W27C01 Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C01 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VDD and Vss. This high frequency, low inherent-inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VDD and Vss. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES VDD = 5.0V ±5%, Vpp = VpE = VHH = 12V, VCP = VPE = 5V, X = VIH or VIL MODE PINS #CE #OE #PGM A0 A9 VDD VPP OUTPUTS Read VIL VIL X X X VDD VDD DOUT Output Disable VIL VIH X X X VDD VDD High Z Standby (TTL) VIH X X X X VDD VDD High Z VDD ±0.3V X X X X VDD VDD High Z Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCP VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VPE VCP VPE FF (Hex) Erase Verify VIL VIL VIH X X VPE VPE DOUT Erase Inhibit VIH X X X X VCP VPE High Z Product Identifier-manufacturer VIL VIL X VIL VHH VDD VDD DA (Hex) Product Identifier-device VIL VIL X VIH VHH VDD VDD 01 (Hex) Standby (CMOS) -3- Publication Release Date: April 15, 2002 Revision A2 W27C01 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Operation Temperature Storage Temperature Voltage on all Pins with Respect to Ground Except VDD, VPP and A9 Pins RATING UNIT 0 to +70 °C -65 to +125 °C -0.5 to VDD +0.5 V Voltage on VDD Pin with Respect to Ground -0.5 to +7.0 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. CAPACITANCE (VDD = 5.0V ±5%, TA = 25° C, f = 1 MHz) CONDITIONS MAX. UNIT Input Capacitance PARAMETER SYMBOL CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF READ OPERATION DC CHARACTERISTICS (VDD = 5.0V ±5%, TA = 0 to 70° C) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI VIN = 0V to VDD -5 - 5 µA Output Leakage Current ILO VOUT = 0V to VDD -10 - 10 µA Standby VDD Current (TTL input) ISB #CE = VIH - - 1 mA Standby VDD Current (CMOS input) ISB1 #CE = VDD ±0.2V - - 100 µA VDD Operating Current ICC #CE=VIL, IOUT = 0 mA, f = 5 MHz - - 30 mA VPP Operating Current IPP VPP = VDD - - 10 µA Input Low Voltage VIL - -0.3 - 0.8 V - Input High Voltage VIH 2.2 - VDD +0.5 V Output Low Voltage VOL IOL = 1.6 mA - - 0.4 V Output High Voltage VOH IOH = -0.1 mA 2.4 - - V VPP Operating Voltage VPP VDD -0.7 - VDD V - -4- W27C01 Program/Erase DC Characteristics (TA = 25° C, VDD = 5.0V ±5%, VHH = 12V) PARAMETER SYM. CONDITIONS LIMITS Input Load Current ILI VIN = VIL or VIH VDD Program Current ICP #CE = VIL, #OE = VIH, UNIT MIN. TYP. MAX. -10 - 10 µA - - 30 mA - - 30 mA - - 30 mA - - 30 mA #PGM = VIL VDD Erase Current ICE #CE = VIL, #OE = VIH, #PGM = VIL, A9 = VHH VPP Program Current IPP #CE = VIL, #OE = VIH, #PGM = VIL VPP Erase Current IPE #CE = VIL, #OE = VIH, #PGM = VIL, A9 = VHH Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Silicon I.D. Voltage VID - 11.5 12.0 12.5 V A9 Erase Voltage VID - 11.75 12.0 14.25 V VPP Program Voltage VPP - 11.75 12.0 12.25 V VPP Erase Voltage VPE - 11.75 12.0 14.25 V VDD Supply Voltage (Program) VCP - 4.5 5.0 5.5 V VDD Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V VDD Supply Voltage (Erase Verify) VPE - - 5.0 - V Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. -5- Publication Release Date: April 15, 2002 Revision A2 W27C01 AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V/1.5V Output Load CL = 100 pF, IOH/IOL = -0.1 mA/1.6 mA for Read IOH/IOL = -0.4 mA/2.1 mA for Program/Erase AC Test Load and Waveforms +1.3V (IN914) 3.3K ohm DOUT 100 pF (Including Jig and Scope) Output Input Test Points Test Points 3.0V 1.5V 0V -6- 1.5V W27C01 READ OPERATION AC CHARACTERISTICS (VDD = 5.0V ±5%, TA = 0 to 70° C) PARAMETER SYMBOL W27C01-70 UNIT MIN. MAX. Read Cycle Time TRC 70 - nS Chip Enable Access Time TCE - 70 nS Address Access Time TACC - 70 nS Output Enable Access Time TOE - 30 nS #OE High to High-Z Output TDF - 25 nS Output Hold from Address Change TOH 0 - nS Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. AC PROGRAMMING/ERASE CHARACTERISTICS (VDD = 5.0V ±5%, TA = 25° C ) PARAMETER SYMBOL LIMITS UNIT MIN. TYP. MAX. VPP Setup Time TVPS 2.0 - - µS Address Setup Time TAS 2.0 - - µS Data Setup Time TDS 2.0 - - µS #PGM Program Pulse Width TPWP 95 100 105 µS #PGM Erase Pulse Width TPWE 95 100 105 mS Data Hold Time TDH 2.0 - - µS #OE Setup Time TOES 2.0 - - µS Data Valid from #OE TOEV - - 150 nS #OE High to Output High Z TDFP 0 - 130 nS Address Hold Time after #PGM High TAH 0 - - µS Address Hold Time (Erase) TAHE 2.0 - - µS #CE Setup Time TCES 2.0 - - µS Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: April 15, 2002 Revision A2 W27C01 TIMING WAVEFORMS AC Read Waveform VIH Address Address Valid VIL VIH #CE VIL TCE VIH #OE TDF VIL TOE TOH TACC Outputs High Z Valid Output High Z Erase Waveform Read Manufacturer Read Device SID SID A9 = 12.0V VIL Others = VIL Others = VIL VIH Address A0 = VIL A0=VIH Others=VIL TAS TAS Data Blank Check Read Verify Erase Verify Chip Erase A9 = 12.0V Address Stable Address Stable TAS DA TAHC Address Stable TACC TDFP DOUT Data All One TDS TDH DOUT DOUT T AH 12.0V 5V TVPS = VDD VPP VIH TCE #CE VIL TOE TOES TOE TOE VIH #OE VIL #PGM TCES TPWE -8- TOEV W27C01 Timing Waveforms, Continued Programming Waveform Program Verify Program Read Verify VIH Address Stable Address Address Stable Address Valid VIL TDFP TAS Data Data In Stable TDS DOUT TACC DOUT DOUT TAH TDH 12.0V VPP 5.0V 5V TVPS TCES #CE VIH VIL TOE #OE VIH VIL VIH #PGM TOES TOEV TPWP VIL -9- Publication Release Date: April 15, 2002 Revision A2 W27C01 SMART PROGRAMMING ALGORITHM Start Address = First Location VDD = 5V Vpp = 12V X=0 Program One 100 µS Pulse Increment X Yes X = 25? No Fail Verify One Byte Verify One Byte Pass Increment Address No Fail Pass Last Address? Yes VDD = 5V Vpp = 5V Compare All Bytes to Original Data Fail Pass Pass Device - 10 - Fail Device W27C01 SMART ERASE ALGORITHM Start X=0 VDD = 5V Vpp = 12V A9 = 12V; A0 = V IL Chip Erase 100 mS Pulse Address = First Location VDD = 4.5V Vpp = 4.5V Increment X No Compare All Bytes to FFs (HEX) Fail X = 20? Yes Pass Pass Device Fail Device - 11 - Publication Release Date: April 15, 2002 Revision A2 W27C01 ORDERING INFORMATION ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (µA) W27C01-70 70 30 20 600 mil DIP W27C01P-70 70 30 20 32-Lead PLCC W27C01Q-70 70 30 20 32-Lead STSOP PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 12 - W27C01 PACKAGE DIMENSIONS 32-pin P-DIP Dimension in Inches Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 a 1 E Min. Nom. Max. 5.33 0.210 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 1.650 1.660 41.91 42.16 0.590 0.600 0.610 14.99 15.24 15.49 0.540 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0 eA S Dimension in mm Min. Nom. Max. 0.630 0.650 15 0.085 2.16 Notes: 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 16 1 E S c 2 1 A A A L Base Plane Seating Plane B e1 eA a B1 32-lead PLCC HE E 4 1 32 30 Symbol 5 29 D D D G H 21 13 14 c 20 A A1 A2 b1 b c D E e GD GE HD HE L y θ Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.140 0.020 3.56 0.50 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 13.46 10.92 1.42 0.490 0.510 0.530 12.45 12.95 0.390 0.410 0.430 9.91 10.41 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.10 0.004 0° 10° 0° 10° Notes: L 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. 2 A θ e b b1 Seating Plane A 1 A y GE - 13 - Publication Release Date: April 15, 2002 Revision A2 W27C01 Package Dimensions, continued 32-lead STSOP (8 x 14 mm) Dimension in Inches Dimension in mm HD Symbol Min. D c e E b £c A1 A2 A L L1 - 14 - Y A A1 A2 b c D E HD e L L1 Y θ Nom. Max. Min. Nom. Max. 1.20 0.047 0.002 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.009 0.010 0.17 0.22 0.27 0.004 ----- 0.008 0.10 ----- 0.21 0.488 12.40 0.315 8.00 0.551 14.00 0.020 0.020 0.024 0.50 0.028 0.50 0.031 0.000 0 3 1.05 0.60 0.70 0.80 0.004 0.00 5 0 0.10 3 5 W27C01 VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 Apr. 2001 - A2 April 15, 2002 All Modify by W27E01 except VDD = 5.0V ±5% 5 Modify by W27E01 except VIH = 2.2V (min.) for read operation. Initial Issued Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 15 - Publication Release Date: April 15, 2002 Revision A2