Preliminary W27C020 256K × 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C020 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 8 bits that operates on a single 5 volt power supply. The W27C020 provides an electrical chip erase function. FEATURES • • • • • High speed access time: 70/90/120 nS (max.) Read operating current: 30 mA (max.) Erase/Programming operating current: 30 mA (max.) Standby current: 1 mA (max.) Single 5V power supply PIN CONFIGURATIONS Vpp 32 1 • • • A16 2 31 3 30 PGM A17 A12 4 29 A14 A7 5 28 A13 A6 6 27 A5 7 32-pin DIP 26 A4 8 A3 9 A2 10 A1 11 22 A0 12 21 CE Q7 Q0 PGM Vcc A15 CE A0 . 24 OE A17 23 A10 13 20 Q6 Q1 14 19 Q5 Q2 15 18 Q4 GND 16 17 Q3 3 2 1 3 3 3 2 1 0 29 28 27 26 32-pin PLCC 25 24 23 1 1 1 1 1 2 22 5 6 7 8 9 0 21 . Q7 OE A8 25 OUTPUT BUFFER CONTROL A9 A11 Q0 4 5 6 7 8 9 10 11 12 1 13 4 • +14V erase/+12V programming voltage Fully static operation All inputs and outputs directly TTL/CMOS compatible Three-state outputs Available packages: 32-pin 600 mil DIP and PLCC BLOCK DIAGRAM CORE DECODER ARRAY VCC GND VPP PIN DESCRIPTION / A A A V V P A 1 1 1 p c G 1 2 5 6 p c M 7 A7 A6 A5 A4 A3 A2 A1 A0 Q0 • SYMBOL A14 A13 A8 A9 A11 OE A10 CE Q7 A0−A17 Address Inputs Q0−Q7 Data Inputs/Outputs CE Chip Enable OE Output Enable PGM VPP VCC GND Q Q G Q Q Q Q 1 2 N 3 4 5 6 D -1- DESCRIPTION Program Enable Program/Erase Supply Voltage Power Supply Ground Publication Release Date: September 1998 Revision A1 Preliminary W27C020 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C020 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C020 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE = VIL, (0.8V or below but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VID (14V), A0 = VIL, and all other address pins equal VIL and data input pins equal VIH. Pulsing PGM low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE = VIL, and OE = VIL, PGM = VIH. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE = VIL, OE = VIH, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing PGM low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE = VIL, OE = VIL, and PGM = VIH. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the CE, the W27C020 may have common inputs. -2- Preliminary W27C020 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In standby mode, all outputs are in a high impedance state, independent of OE and PGM. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C020 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, VID = 14V, X = VIH or VIL MODE PINS CE OE PGM A0 A9 VCC VPP OUTPUTS Read VIL VIL X X X VCC VCC DOUT Output Disable VIL VIH X X X VCC VCC High Z Standby (TTL) VIH X X X X VCC VCC High Z VCC ±0.3V X X X X VCC VCC High Z Program VIL VIH VIL X X VCP VPP DIN Program Verify VIL VIL VIH X X VCC VPP DOUT Program Inhibit VIH X X X X VCP VPP High Z Erase VIL VIH VIL VIL VID VCE VPE FF (Hex) Erase Verify VIL VIL VIH X X VCC VPE DOUT Erase Inhibit VIH X X X X VCE VPE High Z Product Identifiermanufacturer VIL VIL X VIL VHH VCC VCC DA (Hex) Product Identifier-device VIL VIL X VIH VHH VCC VCC 85 (Hex) Standby (CMOS) -3- Publication Release Date: September 1998 Revision A1 Preliminary W27C020 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Ambient Temperature with Power Applied -55 to +125 °C Storage Temperature -65 to +125 °C -0.5 to VCC +0.5 V Voltage on VCC Pin with Respect to Ground -0.5 to +7 V Voltage on VPP Pin with Respect to Ground -0.5 to +14.5 V Voltage on A9 Pin with Respect to Ground -0.5 to +14.5 V Voltage on all Pins with Respect to Ground Except VCC, VPP and A9 Pins Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ±5%, VHH = 14V) PARAMETER SYM. CONDITIONS Input Load Current ILI VIN = VIL or VIH VCC Erase Current ICP CE = VIL, OE = VIH, LIMITS UNI T MIN. TYP. MAX. -10 - 10 µA - - 30 mA - - 30 mA PGM = VIL, A9 = VHH VPP Erase Current IPP CE = VIL, OE = VIH, PGM = VIL, A9 = VHH Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.4 - 5.5 V Output Low Voltage (Verify) VOL IOL = 2.1 mA - - 0.45 V Output High Voltage (Verify) VOH IOH = -0.4 mA 2.4 - - V A9 Erase Voltage VID - 13.75 14.0 14.25 V VPP Erase Voltage VPE - 13.75 14.0 14.25 V VCC Supply Voltage (Erase) VCE - 4.5 5.0 5.5 V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -4- Preliminary W27C020 CAPACITANCE (VCC = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Output Capacitance COUT VOUT = 0V 12 pF AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS 70 nS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0 to 3.0V 5 nS 1.5V/1.5V CL = 30 pF, IOH/IOL = -0.4 mA/2.1 mA 90/120 nS 0.45V to 2.4V 10 nS 0.8V/2.0V CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA AC Test Load and Waveforms +1.3V (IN914) 3.3K ohm DOUT 100 pF for 90/120 nS (Including Jig and Scope) 30 pF for 70 nS (Including Jig and Scope) Input/Output Test Points 2.4V For 90/120 nS 0.45V Test Points 2.0V 2.0V 0.8V 0.8V Test Point Test Point 3.0V For 70 nS 1.5V 1.5V 0V -5- Publication Release Date: September 1998 Revision A1 Preliminary W27C020 READ OPERATION DC CHARACTERISTICS (Vcc = 5.0V ±5%) PARAMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MAX. Input Load Current ILI VIN = 0V to VCC -5 - 5 µA Output Leakage Current ILO VOUT = 0V to VCC -10 - 10 µA Standby VCC Current (TTL input) ISB CE = VIH - - 1.0 mA Standby VCC Current (CMOS input) ISB1 CE = VCC ±0.2V - 5 100 µA VCC Operating Current ICC CE = VIL IOUT = 0 mA f = 5 MHz - - 30 mA VPP Operating Current IPP VPP = VCC - - 10 µA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.2 - VCC +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V VPP Operating Voltage VPP VCC -0.7 - VCC V - READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±5%, for 70, 90 and 120 nS; TA = 0 to 70° C) PARAMETER SYM. W27C020-70 W27C020-90 W27C020-12 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TACC - 70 - 90 - 120 nS Output Enable Access Time TOE - 30 - 40 - 55 nS OE High to High-Z Output TDF - 25 - 25 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -6- Preliminary W27C020 DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. Input Load Current ILI VCC Program Current ICP CONDITIONS LIMITS UNIT MIN. TYP. MAX. VIN = VIL or VIH - - CE = VIL, OE = VIH, - - ±10 30 µA mA - - 30 mA PGM = VIL VPP Program Current IPP CE = VIL, OE = VIH, Input Low Voltage Input High Voltage Output Low Voltage (Verify) VIL VIH VOL PGM = VIL IOL = 2.1 mA -0.3 2.4 - - 0.8 5.5 0.45 V V V Output High Voltage (Verify) A9 Silicon I. D. Voltage VPP Program Voltage VCC Supply Voltage (Program) VOH VID VPP VCP IOH = -0.4 mA - 2.4 11.5 11.75 4.5 12.0 12.0 5.0 12.5 12.25 5.5 V V V V AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. LIMITS UNIT MIN. TYP. MAX. VPP Setup Time TVPS 2.0 - - µS Address Setup Time TAS 2.0 - - µS Data Setup Time TDS 2.0 - - µS PGM Program Pulse Width TPWP 95 100 105 µS PGM Erase Pulse Width Data Hold Time TPWE 95 100 105 mS TDH 2.0 - - µS OE Setup Time TOES 2.0 - - µS Data Valid from OE TOEV - - 150 nS OE High to Output High Z TDFP 0 - 130 nS Address Hold Time after PGM High Address Hold Time (Erase) TAH 0 - - µS TAHE 2.0 - - µS CE Setup Time TCES 2.0 - - µS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: September 1998 Revision A1 Preliminary W27C020 TIMING WAVEFORMS AC Read Waveform VIH Address Address Valid VIL VIH CE VIL TCE VIH TDF OE VIL TOE TOH TACC Outputs High Z Valid Output High Z Erase Waveform Read Manufacturer Read Device SID SID A9 = 12.0V VIL Others = V IL Others = V IL VIH Address A0 = V IL A0=V IH Others=V IL TAS TAS Data DA Blank Check Read Verify Erase Verify Chip Erase A9 = 14.0V Address Stable Address Stable TAS 01 TAHC Address Stable TACC TDFP DOUT Data All One TDS TDH DOUT DOUT T AH 14.0V 5V 5.0V TVPS VPP VIH CE TCE VIL TOE TOES TOE TOE VIH OE VIL TCES TPWE PGM -8- TOEV Preliminary W27C020 Timing Waveforms, continued Programming Waveform Program Verify Program Read Verify VIH Address Stable Address Address Valid Address Stable VIL TDFP TAS Data Data In Stable TDS DOUT TACC DOUT DOUT TAH TDH 12.0V VPP 5.0V VIH 5V TVPS TCES CE VIL TOE VIH OE VIL VIH PGM TOES TOEV TPWP VIL -9- Publication Release Date: September 1998 Revision A1 Preliminary W27C020 SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X=0 Program One 100 µS Pulse Increment X Yes X = 25? No Fail Verify One Byte Verify One Byte Pass Increment Address No Fail Pass Last Address? Yes Vcc = 5V Vpp = 5V Compare All Bytes to Original Data Fail Pass Fail Device Pass Device - 10 - Preliminary W27C020 SMART ERASE ALGORITHM Start X=0 Vcc = 5V Vpp = 14V A9 = 14V; A0 = VIL Chip Erase 100 mS Pulse Address = First Location Increment X No Erase Verify Fail X = 20? Pass Yes Increment Address No Last Address? Yes Vcc = 5V Vpp = 5V Compare All Bytes to FFs (HEX) Fail Pass Pass Device Fail Device - 11 - Publication Release Date: September 1998 Revision A1 Preliminary W27C020 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VCC CURRENT MAX. (µA) PACKAGE W27C20-70 70 30 100 600 mil DIP W27C020-90 90 30 100 600 mil DIP W27C020-12 120 30 100 600 mil DIP W27C020P-70 70 30 100 32-pin PLCC W27C020P-90 90 30 100 32-pin PLCC W27C020P-12 120 30 100 32-pin PLCC Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 12 - Preliminary W27C020 PACKAGE DIMENSIONS 32-pin P-DIP Dimension in Inches Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 5.33 0.210 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.010 0.014 0.20 0.25 0.36 1.650 1.660 41.91 42.16 0.590 0.600 0.610 14.99 15.24 15.49 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0.008 0 a eA S Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.630 0.650 15 0.085 2.16 16 1 Notes: E S c A A2 A1 L Base Plane Seating Plane B e1 eA a B1 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 32-Lead PLCC HE E 4 1 32 30 Symbol 5 29 GD D HD 21 13 14 c 20 A A1 A2 b1 b c D E e GD GE HD HE L y θ Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 3.56 0.140 0.50 0.020 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 13.97 14.05 11.43 11.51 0.550 0.553 13.89 0.447 0.450 0.453 11.35 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.004 0° 10° 0.10 0° 10° Notes: L A2 θ e b b1 Seating Plane A 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. A1 y GE - 13 - Publication Release Date: September 1998 Revision A1 Preliminary W27C020 VERSION HISTORY VERSION DATE A1 Sep. 1998 PAGE DESCRIPTION Initial Issued Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 14 - Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798