MOTOROLA MC68HC705KJ1CS

MC68HC705KJ1/D
Rev. 2.0
HC 5
MC68HC705KJ1
MC68HSC705KJ1
MC68HRC705KJ1
MC68HLC705KJ1
HCMOS Microcontroller Unit
TECHNICAL DATA BOOK
Technical Data
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
© Motorola, Inc., 2000
Technical Data
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MC68HC705KJ1 — Rev. 2.0
Technical Data
MOTOROLA
Technical Data — MC68HC705KJ1
List of Sections
Section 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 23
Section 3. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Section 4. Central Processor Unit (CPU) . . . . . . . . . . . . 41
Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 63
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 73
Section 7. Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . 81
Section 8. Computer Operating Properly
Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . 93
Section 9. External Interrupt Module (IRQ) . . . . . . . . . . . 97
Section 10. Multifunction Timer Module . . . . . . . . . . . . 105
Section 11. Electrical Specifications . . . . . . . . . . . . . . . 113
Section 12. Mechanical Specifications . . . . . . . . . . . . . 127
Section 13. Ordering Information . . . . . . . . . . . . . . . . . 131
Appendix A. MC68HRC705KJ1 . . . . . . . . . . . . . . . . . . . 133
Appendix B. MC68HLC705KJ1. . . . . . . . . . . . . . . . . . . . 139
MC68HC705KJ1 — Rev. 2.0
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Technical Data
List of Sections
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List of Sections
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MC68HC705KJ1 — Rev. 2.0
List of Sections
MOTOROLA
Technical Data — MC68HC705KJ1
Table of Contents
Section 1. Introduction
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Section 2. Pin Descriptions
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.2.1
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.2.2
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .26
2.3.2.3
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.2.4
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.5
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.6
PB2 and PB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
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Table of Contents
Section 3. Memory
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.4
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . .33
3.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6.1
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . .36
3.6.2
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . .36
3.6.3
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.7
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.8
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . .40
Section 4. Central Processor Unit (CPU)
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.4
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.5
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.6.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.6.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.6.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.6.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.6.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .47
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4.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.1.7
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.1.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.2
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.7.2.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . .51
4.7.2.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . .52
4.7.2.3
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . .53
4.7.2.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .55
4.7.2.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.7.3
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Section 5. Resets and Interrupts
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.3.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.3.3
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.4.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.4.2
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.3.1
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.3.2
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
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Section 6. Low-Power Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.3
Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.4
Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.1
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.1.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.1.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.2
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.2.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.2.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.3
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.3.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.3.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.4
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.4.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.4.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.5
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.5.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.5.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.6
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Section 7. Parallel I/O Ports
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.3.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.3.4
Port LED Drive Capability. . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.3.5
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
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7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.4.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.5
I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .90
Section 8. Computer Operating Properly Module (COP)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2
COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . .94
8.4.3
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .95
8.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.6
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Section 9. External Interrupt Module (IRQ)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
9.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
9.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
9.4.1
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
9.4.2
Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . .101
9.5
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .102
9.6
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
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Section 10. Multifunction Timer Module
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
10.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
10.6 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
10.6.1 Timer Status and Control Register . . . . . . . . . . . . . . . . . . .108
10.6.2 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .110
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
10.7.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
10.7.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Section 11. Electrical Specifications
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
11.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
11.3
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .115
11.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.5
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.6
5.0-V DC Electrical Characteristics
11.7
3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .118
11.8
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
11.9
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
. . . . . . . . . . . . . . . . . . .117
11.10 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . .122
11.11 Control Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
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Section 12. Mechanical Specifications
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.2.1 16-Pin PDIP — Case #648. . . . . . . . . . . . . . . . . . . . . . . . .128
12.2.2 16-Pin SOIC — Case #751G . . . . . . . . . . . . . . . . . . . . . . .128
12.2.3 16-Pin Cerdip — Case #620A . . . . . . . . . . . . . . . . . . . . . .129
Section 13. Ordering Information
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.3
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Appendix A. MC68HRC705KJ1
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
A.3
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .134
A.4
Typical Internal Operating Frequency for
RC Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.5
RC Oscillator Connections (No External Resistor) . . . . . . . . .136
A.6
Typical Internal Operating Frequency Versus Temperature
(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.7
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .138
Appendix B. MC68HLC705KJ1
B.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .139
B.4
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .140
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Table of Contents
11
Table of Contents
Technical Data
12
MC68HC705KJ1 — Rev. 2.0
Table of Contents
MOTOROLA
Technical Data — MC68HC705KJ1
List of Figures
Figure
Title
1-1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-1
2-2
2-3
2-7
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . .25
Crystal Connections with
Oscillator Internal Resistor Mask Option . . . . . . . . . . . . .26
Crystal Connections without
Oscillator Internal Resistor Mask Option . . . . . . . . . . . . .26
Ceramic Resonator Connections with
Oscillator Internal Resistor Mask Option . . . . . . . . . . . . .27
Ceramic Resonator Connections without
Oscillator Internal Resistor Mask Option . . . . . . . . . . . . .27
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . .28
3-1
3-2
3-3
3-4
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EPROM Programming Register (EPROG) . . . . . . . . . . . . . .36
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . .38
4-1
4-2
4-3
4-4
4-5
4-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .47
2-4
2-5
2-6
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Page
Technical Data
List of Figures
13
List of Figures
Figure
Title
5-1
5-2
5-3
5-4
5-5
5-6
5-7
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .68
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6-1
6-2
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . .79
STOP/HALT/WAIT Flowchart . . . . . . . . . . . . . . . . . . . . . . . .80
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
Parallel I/O Port Register Summary . . . . . . . . . . . . . . . . . . .82
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .83
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .83
Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .85
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .86
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .87
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .89
8-1
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
9-1
9-2
9-3
9-4
9-5
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .99
IRQ Module I/O Register Summary . . . . . . . . . . . . . . . . . . .99
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .102
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .104
10-1
10-2
10-3
10-4
Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . .106
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Timer Status and Control Register (TSCR) . . . . . . . . . . . .108
Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . .110
Technical Data
14
Page
MC68HC705KJ1 — Rev. 2.0
List of Figures
MOTOROLA
List of Figures
Figure
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
A-1
A-2
A-3
A-4
B-1
Title
PA4–PA7 Typical High-Side Driver Characteristics . . . . . .119
PA0–PA3 and PB2–PB3 Typical High-Side
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .119
PA4–PA7 Typical Low-Side Driver Characteristics . . . . . .120
PA0–PA3 and PB2–PB3 Typical Low-Side
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .120
Typical Operating IDD (25°C) . . . . . . . . . . . . . . . . . . . . . . .121
Typical Wait Mode IDD (25°C) . . . . . . . . . . . . . . . . . . . . . .122
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .125
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . .125
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .126
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . .134
Typical Internal Operating Frequency for
Various VDD at 25°C — RC Oscillator Option Only . . . .135
RC Oscillator Connections (No External Resistor) . . . . . . .136
Typical Internal Operating Frequency
Versus Temperature (OSCRES Bit = 1) . . . . . . . . . . . .137
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Page
Technical Data
List of Figures
15
List of Figures
Technical Data
16
MC68HC705KJ1 — Rev. 2.0
List of Figures
MOTOROLA
Technical Data — MC68HC705KJ1
List of Tables
Table
Title
1-1
Programmable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3-1
EPROM Programming Characteristics . . . . . . . . . . . . . . . . .40
4-1
4-2
4-3
4-4
4-5
4-6
4-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .51
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .52
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .54
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .55
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5-1
5-2
5-3
5-4
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
External Interrupt Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . .68
External Interrupt Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . .68
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . .71
7-1
7-2
7-3
7-4
Port A Pin Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Port B Pin Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
I/O Port DC Electrical Characteristics (VDD = 5.0 V) . . . . . .90
I/O Port DC Electrical Characteristics (VDD = 3.3 V) . . . . . .91
9-1
9-2
9-3
I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . .99
External Interrupt Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . .104
External Interrupt Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . .104
10-1
10-2
I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . .107
Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . .110
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Page
Technical Data
List of Tables
17
List of Tables
Table
Title
11-1
11-2
11-3
Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Control Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . .123
Control Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . .124
13-1
Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
A-1
MC68HRC705KJ1 (RC Oscillator Option)
Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
B-1
B-2
B-3
DC Electrical Characteristics (VDD = 5 V) . . . . . . . . . . . . .139
DC Electrical Characteristics (VDD = 3.3 V) . . . . . . . . . . . .139
MC68HLC705KJ1 (High Speed) Order Numbers . . . . . . .140
Technical Data
18
Page
MC68HC705KJ1 — Rev. 2.0
List of Tables
MOTOROLA
Technical Data — MC68HC705KJ1
Section 1. Introduction
1.1 Contents
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.3
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.2 Features
Features on the MC68HC705KJ1 include:
•
Robust Noise Immunity
•
4.0-MHz Internal Operating Frequency at 5.0 V
•
1240 Bytes of EPROM/OTPROM (Electrically Programmable
Read-Only Memory/One-Time Programmable Read-Only
Memory), Including Eight Bytes for User Vectors
•
64 Bytes of User RAM
•
Peripheral Modules
– 15-Stage Multifunction Timer
– Computer Operating Properly (COP) Watchdog
•
10 Bidirectional Input/Output (I/O) Lines, Including:
– 10-mA Sink Capability on All I/O Pins
– Software Programmable Pulldowns on All I/O Pins
– Keyboard Scan with Selectable Interrupt on Four I/O Pins
– 5.5-mA Source Capability on Six I/O Pins
•
Selectable Sensitivity on External Interrupt (Edge- and
Level-Sensitive or Edge-Sensitive Only)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Introduction
19
Introduction
•
On-Chip Oscillator with Connections for:
– Crystal
– Ceramic Resonator
– Resistor-Capacitor (RC) Oscillator (MC68HRC705KJ1) with or
without External Resistor
– External Clock
– Low-Speed (32-kHz) Crystal (MC68HLC705KJ1)
•
Memory-Mapped I/O Registers
•
Fully Static Operation with No Minimum Clock Speed
•
Power-Saving Stop, Halt, Wait, and Data-Retention Modes
•
External Interrupt Mask Bit and Acknowledge Bit
•
Illegal Address Reset
•
Internal Steering Diode and Pullup Resistor from RESET Pin to
VDD
•
Selectable EPROM Security1
•
Selectable Oscillator Bias Resistor
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
Technical Data
20
MC68HC705KJ1 — Rev. 2.0
Introduction
MOTOROLA
Introduction
Structure
1.3 Structure
OSC1
OSC2
INTERNAL
OSCILLATOR
15-STAGE
MULTIFUNCTION
TIMER SYSTEM
DIVIDE
BY 2
CPU CONTROL
ALU
68HC05 CPU
IRQ/VPP
ACCUMULATOR
CPU REGISTERS
INDEX REGISTER
0 0 0 0 0 0 0 0 1 1 STK PTR
PB3(1)
PORT B
RESET
DATA DIRECTION REGISTER B
WATCHDOG AND
ILLEGAL ADDRESS
DETECT
PB2(1)
STATIC RAM (SRAM) – 64 BYTES
USER EPROM – 1240 BYTES
PA7
PA6
PA5
PORT A
CONDITION CODE
REGISTER 1 1 1 H I N Z C
DATA DIRECTION REGISTER A
PROGRAM COUNTER
PA4
PA3(1) (2)
PA2(1) (2)
PA1(1) (2)
PA0(1) (2)
10-mA sink capability on all I/O pins
MASK OPTION REGISTER (MOR)
Notes:
1. 5.5 mA source capability
2. External interrupt capability
Figure 1-1. Block Diagram
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Introduction
21
Introduction
1.4 Programmable Options
The options in Table 1-1 are programmable in the mask option register.
Table 1-1. Programmable Options
Feature
Option
COP Watchdog Timer
Enabled or Disabled
External Interrupt Triggering
Edge-Sensitive Only or Edge- and Level-Sensitive
Port A IRQ Pin Interrupts
Enabled or Disabled
Port Pulldown Resistors
Enabled or Disabled
STOP Instruction Mode
Stop Mode or Halt Mode
Crystal Oscillator Internal Resistor Enabled or Disabled
EPROM Security
Enabled or Disabled
Short Oscillator Delay Counter
Enabled or Disabled
Technical Data
22
MC68HC705KJ1 — Rev. 2.0
Introduction
MOTOROLA
Technical Data — MC68HC705KJ1
Section 2. Pin Descriptions
2.1 Contents
2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.2.1
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.2.2
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .26
2.3.2.3
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.2.4
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.5
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.6
PB2 and PB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Pin Descriptions
23
Pin Descriptions
2.2 Pin Assignments
RESET
1
16
IRQ/VPP
OSC1
2
15
PA0
OSC2
3
14
PA1
PB3
4
13
PA2
PB2
5
12
PA3
VDD
6
11
PA4
VSS
7
10
PA5
PA7
8
9
PA6
Figure 2-1. Pin Assignments
2.3 Pin Functions
The pin functions of the MCUs are described in these subsections.
2.3.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Very fast signal transitions occur on the MCU pins, placing high,
short-duration current demands on the power supply. To prevent noise
problems, take special care, as Figure 2-2 shows, by placing the bypass
capacitors as close as possible to the MCU. C2 is an optional bulk
current bypass capacitor for use in applications that require the port pins
to source high current levels.
Technical Data
24
MC68HC705KJ1 — Rev. 2.0
Pin Descriptions
MOTOROLA
Pin Descriptions
Pin Functions
V+
VDD
VDD
MCU
C1
0.1 µF
C2
+
C2
C1
VSS
VSS
Figure 2-2. Bypassing Layout Recommendation
2.3.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
The oscillator can be driven by any of the following:
1. Standard crystal (See Figure 2-3 and Figure 2-4.)
2. Ceramic resonator (See Figure 2-5 and Figure 2-6.)
3. Resistor/capacitor (RC) oscillator (Refer to Appendix A.
MC68HRC705KJ1.)
4. External clock signal as shown in (See Figure 2-7.)
5. Low speed (32 kHz) crystal connections (Refer to Appendix B.
MC68HLC705KJ1.)
The frequency, fOSC, of the oscillator or external clock source is divided
by two to produce the internal operating frequency, fOP.
2.3.2.1 Crystal Oscillator
Figure 2-3 and Figure 2-4 show a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable startup and maximum
stability. The load capacitance values used in the oscillator circuit design
should include all stray layout capacitances.
To minimize output distortion, mount the crystal and capacitors as close
as possible to the pins. An internal startup resistor of approximately
2 MΩ is provided between OSC1 and OSC2 for the crystal oscillator as
a programmable mask option.
NOTE:
Use an AT-cut crystal and not an AT-strip crystal because the MCU can
overdrive an AT-strip crystal.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Pin Descriptions
25
Pin Descriptions
VSS
MCU
C3
PA7
PA7
OSC2
XTAL
OSC2
C4
XTAL
C3
27 pF
C4
27 pF
VDD
C2
C1
VSS
Figure 2-3. Crystal Connections with
Oscillator Internal Resistor Mask Option
VSS
C3
MCU
R
10 MΩ
OSC2
PA7
PA7
XTAL
R
OSC2
C4
VDD
XTAL
C3
27 pF
C4
27 pF
C2
C1
VSS
Figure 2-4. Crystal Connections without
Oscillator Internal Resistor Mask Option
2.3.2.2 Ceramic Resonator Oscillator
To reduce cost, use a ceramic resonator instead of the crystal. The
circuits shown in Figure 2-5 and Figure 2-6 show ceramic resonator
circuits. Follow the resonator manufacturer’s recommendations, as the
resonator parameters determine the external component values
required for maximum stability and reliable starting. The load
capacitance values used in the oscillator circuit design should include all
stray capacitances.
Technical Data
26
MC68HC705KJ1 — Rev. 2.0
Pin Descriptions
MOTOROLA
Pin Descriptions
Pin Functions
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ is provided between OSC1 and OSC2 as
a programmable mask option.
VSS
MCU
PA7
CERAMIC
RESONATOR
OSC2
PA7
CERAMIC
RESONATOR
C3
27 pF
C3
OSC2
C4
C4
27 pF
VDD
C2
C1
VSS
Figure 2-5. Ceramic Resonator Connections with
Oscillator Internal Resistor Mask Option
VSS
C3
CERAMIC
RESONATOR
R
10 MΩ
OSC2
PA7
MCU
PA7
R
OSC2
C4
C3
27 pF
CERAMIC
RESONATOR
VDD
C4
27 pF
C2
C1
VSS
Figure 2-6. Ceramic Resonator Connections without
Oscillator Internal Resistor Mask Option
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Pin Descriptions
27
Pin Descriptions
2.3.2.3 RC Oscillator
Refer to Appendix A. MC68HRC705KJ1.
2.3.2.4 External Clock
An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 2-7. This configuration is possible regardless of
whether the crystal/ceramic resonator or the RC oscillator is enabled.
OSC2
PA7
MCU
EXTERNAL
CMOS CLOCK
Figure 2-7. External Clock Connections
2.3.3 RESET
Applying a logic 0 to the RESET pin forces the MCU to a known startup
state. An internal reset also pulls the RESET pin low. An internal resistor
to VDD pulls the RESET pin high. A steering diode between the RESET
and VDD pins discharges any RESET pin voltage when power is
removed from the MCU. The RESET pin contains an internal Schmitt
trigger to improve its noise immunity as an input. Refer to Section 5.
Resets and Interrupts for more information.
Technical Data
28
MC68HC705KJ1 — Rev. 2.0
Pin Descriptions
MOTOROLA
Pin Descriptions
Pin Functions
2.3.4 IRQ/VPP
The external interrupt/programming voltage pin (IRQ/VPP) drives the
asynchronous IRQ interrupt function of the CPU. Additionally, it is used
to program the user EPROM and mask option register. (See Section 3.
Memory and Section 9. External Interrupt Module (IRQ).)
The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/VPP input requires an
external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not
used, it must be tied to the VDD supply.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. The voltage on this pin should not exceed
VDD except when the pin is being used for programming the EPROM.
NOTE:
The mask option register can enable the PA0–PA3 pins to function as
external interrupt pins.
2.3.5 PA0–PA7
These eight input/output (I/O) lines comprise port A, a general-purpose
bidirectional I/O port. (See Section 9. External Interrupt Module (IRQ)
for information on PA0–PA3 external interrupts.)
2.3.6 PB2 and PB3
These two I/O lines comprise port B, a general-purpose bidirectional
I/O port.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Pin Descriptions
29
Pin Descriptions
Technical Data
30
MC68HC705KJ1 — Rev. 2.0
Pin Descriptions
MOTOROLA
Technical Data — MC68HC705KJ1
Section 3. Memory
3.1 Contents
3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.4
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . .33
3.5
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6.1
EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . .36
3.6.2
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . .36
3.6.3
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.7
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.8
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . .40
3.2 Features
Memory features include:
•
1232 Bytes of User EPROM, Plus Eight Bytes for User Vectors
•
64 Bytes of User RAM
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Memory
31
Memory
3.3 Memory Map
Port A Data Register (PORTA)
Port B Data Register (PORTB)
Unimplemented
Data Direction Register A (DDRA)
Data Direction Register B (DDRB)
Unimplemented
$0000
↓
$001F
$0020
↓
$00BF
$00C0
↓
$00FF
$0100
↓
$02FF
$0300
↓
$07CF
$07D0
↓
$07ED
$07EE
$07EF
$07F0
↓
$07FF
Timer Status and Control Register (TSCR)
Timer Control Register (TCR)
IRQ Status and Control Register (ISCR)
I/O Registers
32 Bytes
Unimplemented
Unimplemented
160 Bytes
Pulldown Register Port A (PDRA)
Pulldown Register Port B (PDRB)
RAM
64 Bytes
Unimplemented
EPROM Programming Register (EPROG)
Unimplemented
512 Bytes
Unimplemented
EPROM
1232 Bytes
Reserved
COP Register (COPR)(1)
Mask Option Register (MOR)
Unimplemented
30 Bytes
Reserved
Test ROM
2 Bytes
Timer Interrupt Vector High
Timer Interrupt Vector Low
External Interrupt Vector High
External Interrupt Vector Low
Software Interrupt Vector High
Software Interrupt Vector Low
Reset Vector High
Reset Vector Low
Registers and EPROM
16 Bytes
(1)Writing
$07F0
$07F1
$07F2
↓
$07F7
$07F8
$07F9
$07FA
$07FB
$07FC
$07FD
$07FE
$07FF
to bit 0 of $07F0 clears the COP watchdog.
Figure 3-1. Memory Map
Technical Data
32
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
↓
$000F
$0010
$0011
$0012
↓
$0017
$0018
$0019
↓
$001E
$001F
MC68HC705KJ1 — Rev. 2.0
Memory
MOTOROLA
Memory
Input/Output Register Summary
3.4 Input/Output Register Summary
Addr.
$0000
$0001
Register Name
Port A Data Register Read:
(PORTA) Write:
See page 83. Reset:
Port B Data Register Read:
(PORTB) Write:
See page 86. Reset:
$0002
Unimplemented
$0003
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Unaffected by Reset
0
Refer to Section 7.
Parallel I/O Ports
PB3
PB2
Refer to Section 7.
Parallel I/O Ports
Unaffected by Reset
Data Direction Register A Read: DDRA7
$0004
(DDRA) Write:
See page 83. Reset:
0
Data Direction Register B Read:
$0005
(DDRB) Write:
See page 87. Reset:
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB3
DDRB2
0
0
0
0
TOFR
RTIFR
0
0
0
0
RTIF
Refer to Section 7.
Parallel I/O Ports
0
0
TOIE
RTIE
Refer to Section 7.
Parallel I/O Ports
0
0
RT1
RT0
$0006
Unimplemented
$0007
Unimplemented
TOF
$0008
Timer Status and Control Read:
Register (TSCR) Write:
See page 108. Reset:
0
0
0
0
0
0
1
1
Timer Counter Register Read:
(TCR) Write:
See page 110. Reset:
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
0
0
0
0
0
0
0
0
0
0
0
IRQF
0
0
0
$0009
$000A
IRQ Status and Control Read:
Register (ISCR) Write:
See page 102. Reset:
IRQE
1
R
0
0
= Unimplemented
0
R = Reserved
IRQR
0
0
0
0
U = Unaffected
Figure 3-2. I/O Register Summary (Sheet 1 of 2)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Memory
33
Memory
Addr.
Register Name
$000B
Bit 7
6
5
4
3
2
1
Bit 0
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
0
0
0
0
0
0
0
0
PDIB3
PDIB2
0
0
0
ELAT
MPGM
EPGM
Unimplemented
↓
$000F
Unimplemented
$0010
Pulldown Register Port A Read:
(PDRA) Write:
See page 85. Reset:
$0011
Read:
Pulldown Register Port B
(PDRB) Write:
See page 89.
Reset:
$0012
Refer to Section 7.
Parallel I/O Ports
Refer to Section 7.
Parallel I/O Ports
0
0
0
0
0
0
0
0
0
0
R
R
R
R
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Unimplemented
↓
$0017
Unimplemented
$0018
EPROM Programming Read:
Register (EPROG) Write:
See page 36. Reset:
$0019
Unimplemented
↓
$001E
Unimplemented
$001F
Reserved
$07F0
$07F1
Read:
COP Register (COPR)
Write:
See page 95.
Reset:
COPC
U
Mask Option Register Read: SOSCD
(MOR) Write:
See page 38. Reset:
U
U
EPMSEC OSCRES
U
U
U
U
0
SWAIT
PDI
PIRQ
LEVEL
COPEN
Unaffected by reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 3-2. I/O Register Summary (Sheet 2 of 2)
Technical Data
34
MC68HC705KJ1 — Rev. 2.0
Memory
MOTOROLA
Memory
RAM
3.5 RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM
and the stack RAM. Before processing an interrupt, the CPU uses five
bytes of the stack to save the contents of the CPU registers. During a
subroutine call, the CPU uses two bytes of the stack to store the return
address. The stack pointer decrements when the CPU stores a byte on
the stack and increments when the CPU retrieves a byte from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
3.6 EPROM/OTPROM
An MCU with a quartz window has 1240 bytes of erasable,
programmable ROM (EPROM). The quartz window allows EPROM
erasure with ultraviolet light.
NOTE:
Keep the quartz window covered with an opaque material except when
erasing the MCU. Ambient light can affect MCU operation.
In an MCU without the quartz window, the EPROM cannot be erased
and serves as 1240 bytes of one-time programmable ROM (OTPROM).
The following addresses are user EPROM/OTPROM locations:
•
$0300–$07CF
•
$07F8–$07FF, used for user-defined interrupt and reset vectors
The COP register (COPR) is an EPROM/OTPROM location at address
$07F0.
The mask option register (MOR) is an EPROM/OTPROM location at
address $07F1.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Memory
35
Memory
3.6.1 EPROM/OTPROM Programming
The two ways to program the EPROM/OTPROM are:
•
Manipulating the control bits in the EPROM programming register
to program the EPROM/OTPROM on a byte-by-byte basis
•
Programming the EPROM/OTPROM with the M68HC705J
In-Circuit Simulator (M68HC705JICS) available from Motorola
3.6.2 EPROM Programming Register
The EPROM programming register (EPROG) contains the control bits
for programming the EPROM/OTPROM.
Address:
Read:
$0018
Bit 7
6
5
4
3
0
0
0
0
0
R
R
R
R
0
0
0
0
= Unimplemented
R
Write:
Reset:
0
2
1
Bit 0
ELAT
MPGM
EPGM
0
0
0
= Reserved
Figure 3-3. EPROM Programming Register (EPROG)
ELAT — EPROM Bus Latch Bit
This read/write bit latches the address and data buses for
EPROM/OTPROM programming. Clearing the ELAT bit automatically
clears the EPGM bit. EPROM/OTPROM data cannot be read while
the ELAT bit is set. Reset clears the ELAT bit.
1 = Address and data buses configured for EPROM/OTPROM
programming the EPROM
0 = Address and data buses configured for normal operation
MPGM — MOR Programming Bit
This read/write bit applies programming power from the IRQ/VPP pin
to the mask option register. Reset clears MPGM.
1 = Programming voltage applied to MOR
0 = Programming voltage not applied to MOR
Technical Data
36
MC68HC705KJ1 — Rev. 2.0
Memory
MOTOROLA
Memory
EPROM/OTPROM
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/VPP pin to the
EPROM. To write the EPGM bit, the ELAT bit must be set already.
Reset clears EPGM.
1 = Programming voltage (IRQ/VPP pin) applied to EPROM
0 = Programming voltage (IRQ/VPP pin) not applied to EPROM
NOTE:
Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets ELAT and clears EPGM. ELAT must be set first by a separate
instruction.
Bits [7:3] — Reserved
Take the following steps to program a byte of EPROM/OTPROM:
1. Apply the programming voltage, VPP, to the IRQ/VPP pin.
2. Set the ELAT bit.
3. Write to any EPROM/OTPROM address.
4. Set the EPGM bit and wait for a time, tEPGM.
5. Clear the ELAT bit.
3.6.3 EPROM Erasing
The erased state of an EPROM bit is logic 0. Erase the EPROM by
exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537
angstroms. Position the ultraviolet light source one inch from the
EPROM. Do not use a shortwave filter.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Memory
37
Memory
3.7 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that
controls the following options:
•
COP watchdog (enable or disable)
•
External interrupt pin triggering (edge-sensitive only or edge- and
level-sensitive)
•
Port A external interrupts (enable or disable)
•
Port pulldown resistors (enable or disable)
•
STOP instruction (stop mode or halt mode)
•
Crystal oscillator internal resistor (enable or disable)
•
EPROM security (enable or disable)
•
Short oscillator delay (enable or disable)
Take the following steps to program the mask option register (MOR):
1. Apply the programming voltage, VPP, to the IRQ/VPP pin.
2. Write to the MOR.
3. Set the MPGM bit and wait for a time, tMPGM.
4. Clear the MPGM bit.
5. Reset the MCU.
Address:
$07F1
Bit 7
6
5
4
3
2
1
Bit 0
SWAIT
SWPDI
PIRQ
LEVEL
COPEN
Read:
SOSCD
EPMSEC OSCRES
Write:
Reset:
Unaffected by reset
Figure 3-4. Mask Option Register (MOR)
Technical Data
38
MC68HC705KJ1 — Rev. 2.0
Memory
MOTOROLA
Memory
Mask Option Register
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The
normal stabilization delay following reset or exit from stop mode is
4064 tcyc. Setting SOSCD enables a 128 tcyc stabilization delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-MΩ internal resistor in the oscillator
circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE:
Program the OSCRES bit to logic 0 in devices using low-speed crystal
or RC oscillators with external resistor.
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 tcyc occurs after
exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Memory
39
Memory
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
3.8 EPROM Programming Characteristics
Table 3-1. EPROM Programming Characteristics(1)
Characteristic
Symbol
Min
Typ
Max
Programming Voltage
IRQ/VPP
VPP
16.0
16.5
17.0
Programming Current
IRQ/VPP
IPP
—
3.0
10.0
tEPGM
tMPGM
4
4
—
—
—
—
Programming Time
Per Array Byte
MOR
Unit
V
mA
ms
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C
Technical Data
40
MC68HC705KJ1 — Rev. 2.0
Memory
MOTOROLA
Technical Data — MC68HC705KJ1
Section 4. Central Processor Unit (CPU)
4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.4
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.5
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.6.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.6.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.6.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.6.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.6.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.1
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.7.1.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.1.7
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.1.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.7.2
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.7.2.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . .51
4.7.2.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . .52
4.7.2.3
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . .53
4.7.2.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .55
4.7.2.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.7.3
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .56
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Central Processor Unit (CPU)
41
Central Processor Unit (CPU)
4.2 Introduction
The central processor unit (CPU) consists of a CPU control unit, an
arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit
fetches and decodes instructions. The ALU executes the instructions.
The CPU registers contain data, addresses, and status bits that reflect
the results of CPU operations.
4.3 Features
Features of the CPU include:
•
4.0-MHz Bus Frequency on Standard Part
•
8-Bit Accumulator
•
8-Bit Index Register
•
11-Bit Program Counter
•
6-Bit Stack Pointer
•
Condition Code Register with Five Status Flags
•
62 Instructions
•
8 Addressing Modes
•
Power-Saving Stop, Wait, Halt, and Data-Retention Modes
Technical Data
42
MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Control Unit
ARITHMETIC/LOGIC UNIT
CPU CONTROL UNIT
7
6
5
4
3
2
1
0
ACCUMULATOR (A)
7
6
5
4
3
2
1
0
INDEX REGISTER (X)
15 14 13 12 11 10
9
8
7
6
0
0
0
0
1
1
15 14 13 12 11 10
9
8
7
6
0
0
0
0
0
0
0
0
5
4
3
2
1
0
STACK POINTER (SP)
5
4
3
2
1
0
0
PROGRAM COUNTER (PC)
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 4-1. Programming Model
4.4 CPU Control Unit
The CPU control unit fetches and decodes instructions during program
operation. The control unit selects the memory locations to read and
write and coordinates the timing of all CPU operations.
4.5 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and
manipulation operations decoded from the instruction set by the CPU
control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register
(CCR).
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Central Processor Unit (CPU)
43
Central Processor Unit (CPU)
4.6 CPU Registers
The M68HC05 CPU contains five registers that control and monitor MCU
operation:
•
Accumulator
•
Index register
•
Stack pointer
•
Program counter
•
Condition code register
CPU registers are not memory mapped.
4.6.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and results of ALU operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 4-2. Accumulator (A)
4.6.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register to determine the conditional address of the operand. The index
register also can serve as a temporary storage location or a counter.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 4-3. Index Register (X)
Technical Data
44
MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
4.6.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset or after the reset stack pointer
instruction (RSP), the stack pointer is preset to $00FF. The address in
the stack pointer decrements after a byte is stacked and increments
before a byte is unstacked.
Read:
Bit
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
5
4
3
2
1
Bit
0
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 4-4. Stack Pointer (SP)
The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
MC68HC705KJ1 — Rev. 2.0
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Technical Data
Central Processor Unit (CPU)
45
Central Processor Unit (CPU)
4.6.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The five most significant bits
of the program counter are ignored and appear as 00000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Reset:
Bit
15
14
13
12
11
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
Bit
0
Loaded with vector from $07FE and $07FF
Figure 4-5. Program Counter (PC)
Technical Data
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MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
4.6.5 Condition Code Register
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
Read:
Bit 7
6
5
1
1
1
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
Write:
Reset:
1
1
1
= Unimplemented
U = Unaffected
Figure 4-6. Condition Code Register (CCR)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The
half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations.
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is logic 1, the interrupt request is latched. Normally, the CPU
processes the latched interrupt request as soon as the interrupt mask
is cleared again.
A return from interrupt instruction (RTI) unstacks the CPU registers,
restoring the interrupt mask to its cleared state. After any reset, the
interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a
negative result.
MC68HC705KJ1 — Rev. 2.0
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Technical Data
Central Processor Unit (CPU)
47
Central Processor Unit (CPU)
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result
of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
4.7 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes.
4.7.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing
modes are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
Technical Data
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MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
4.7.1.1 Inherent
Inherent instructions are those that have no operand, such as
return-from-interrupt (RTI) and stop (STOP). Some of the inherent
instructions act on data in the CPU registers, such as set carry flag
(SEC) and increment accumulator (INCA). Inherent instructions require
no operand address and are one byte long.
4.7.1.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
4.7.1.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
4.7.1.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
4.7.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or input/output
(I/O) location.
MC68HC705KJ1 — Rev. 2.0
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Technical Data
Central Processor Unit (CPU)
49
Central Processor Unit (CPU)
4.7.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
4.7.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
4.7.1.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset because the assembler determines the proper offset
and verifies that it is within the span of the branch.
Technical Data
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Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
4.7.2 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/branch instructions
•
Bit manipulation instructions
•
Control instructions
4.7.2.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 4-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Mnemonic
Technical Data
Central Processor Unit (CPU)
51
Central Processor Unit (CPU)
4.7.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write instructions on registers with
write-only bits.
Table 4-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
Technical Data
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Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
4.7.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
NOTE:
Do not use BRCLR or BRSET instructions on registers with
write-only bits.
MC68HC705KJ1 — Rev. 2.0
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Technical Data
Central Processor Unit (CPU)
53
Central Processor Unit (CPU)
Table 4-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
Technical Data
54
Mnemonic
MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
4.7.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 4-4. Bit Manipulation Instructions
Instruction
Mnemonic
Bit Clear
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Bit Set
NOTE:
BSET
Do not use bit manipulation instructions on registers with write-only bits.
4.7.2.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 4-5. Control Instructions
Instruction
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Mnemonic
Technical Data
Central Processor Unit (CPU)
55
Central Processor Unit (CPU)
4.7.3 Instruction Set Summary
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Description
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
Branch if Carry Bit Clear
— — ↕
0
b7
BCC rel
↕ — ↕
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Right
↕ — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
Clear Bit n
— — ↕
↕
— — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
ff
ff
Cycles
↕
IMM
DIR
EXT
IX2
IX1
IX
Effect on
CCR
H I N Z C
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
BCLR n opr
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Address
Mode
Source
Form
Operand
Table 4-6. Instruction Set Summary (Sheet 1 of 6)
5
3
3
6
5
5
3
3
6
5
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
Technical Data
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MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
H I N Z C
Operand
Cycles
BHI rel
Operation
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 2 of 6)
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
Description
Branch if Higher
Effect on
CCR
BHS rel
Branch if Higher or Same
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
REL
Technical Data
Central Processor Unit (CPU)
57
Central Processor Unit (CPU)
H I N Z C
Operand
Cycles
Operation
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 3 of 6)
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Description
Effect on
CCR
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
(A) – (M)
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
EXCLUSIVE OR Accumulator with Memory Byte
Increment Byte
(X) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
Technical Data
58
3F
4F
5F
6F
7F
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
2
dd
DIR
INH
INH
IX1
IX
— — 0 1 —
— — ↕
2
↕
ff
dd
ff
dd
ff
dd
ff
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
— — — — —
DIR
EXT
IX2
IX1
IX
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
A ← (M)
Load Accumulator with Memory Byte
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
X ← (M)
Load Index Register with Memory Byte
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
C
Logical Shift Left (Same as ASL)
0
b7
MUL
Unsigned Multiply
INH
42
Negate Byte (Two’s Complement)
NOP
No Operation
— — ↕
↕
b0
0
C
b7
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
↕
— — 0
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— — ↕
↕
↕
— — — — —
Logical OR Accumulator with Memory
A ← (A) ∨ (M)
MC68HC705KJ1 — Rev. 2.0
— — ↕
↕ —
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ff
ff
Cycles
Description
Unconditional Jump
Logical Shift Right
MOTOROLA
— — — — —
DIR
EXT
IX2
IX1
IX
Effect on
CCR
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Opcode
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Operation
Address
Mode
Source
Form
Operand
Table 4-6. Instruction Set Summary (Sheet 4 of 6)
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Technical Data
Central Processor Unit (CPU)
59
Central Processor Unit (CPU)
H I N Z C
C
Rotate Byte Left through Carry Bit
— — ↕
b7
↕
↕
b0
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
Cycles
Description
Operand
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 5 of 6)
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
INH
80
9
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
Store Index Register In Memory
Subtract Memory Byte from Accumulator
A ← (A) – (M)
Technical Data
60
↕
↕ —
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
— 0 — — —
INH
8E
— — ↕
— — ↕
— — ↕
ff
5
3
3
6
5
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
↕ —
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
MC68HC705KJ1 — Rev. 2.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
WAIT
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
X ← (A)
(M) – $00
A ← (X)
Stop CPU Clock and Enable Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
— — — — —
INH
83
INH
97
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 4-6. Instruction Set Summary (Sheet 6 of 6)
10
2
dd
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
— — ↕
↕ —
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
Technical Data
Central Processor Unit (CPU)
61
Bit Manipulation
DIR
DIR
MSB
LSB
0
1
2
3
4
Central Processor Unit (CPU)
5
6
7
8
9
A
B
C
MOTOROLA
MC68HC705KJ1 — Rev. 2.0
D
E
F
0
Branch
REL
DIR
2
3
1
Read-Modify-Write
INH
INH
IX1
4
5
6
IX
7
5
5
3
5
3
3
6
5
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BCLR0
BRN
3
DIR 2
DIR 2
REL
1
5
5
3
11
BRSET1
BSET1
BHI
MUL
3
DIR 2
DIR 2
REL
1
INH
5
5
3
5
3
3
6
5
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BCLR5
BMI
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BSET7
BIL
3
DIR 2
DIR 2
REL
1
5
5
3
5
3
3
6
5
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
Control
INH
INH
8
9
9
RTI
INH
6
RTS
INH
2
2
2
10
SWI
INH
2
2
2
2
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
2
STOP
INH
2
2
WAIT
TXA
INH 1
INH
IMM
DIR
A
B
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
MSB
LSB
LSB of Opcode in Hexadecimal
0
Register/Memory
EXT
IX2
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
0
C
D
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
IX1
IX
E
F
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
MSB of Opcode in
Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
MSB
LSB
3
SUB
IX
3
CMP
IX
3
SBC
IX
3
CPX
IX
3
AND
IX
3
BIT
IX
3
LDA
IX
4
STA
IX
3
EOR
IX
3
ADC
IX
3
ORA
IX
3
ADD
IX
2
JMP
IX
5
JSR
IX
3
LDX
IX
4
STX
IX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Central Processor Unit (CPU)
Technical Data
62
Table 4-7. Opcode Map
Technical Data — MC68HC705KJ1
Section 5. Resets and Interrupts
5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.3.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.3.3
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.4.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.4.2
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.3.1
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.3.2
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.2 Introduction
Reset initializes the MCU by returning the program counter to a known
address and by forcing control and status bits to known states.
Interrupts temporarily change the sequence of program execution to
respond to events that occur during processing.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Resets and Interrupts
63
Resets and Interrupts
5.3 Resets
A reset immediately stops the operation of the instruction being
executed, initializes certain control and status bits, and loads the
program counter with a user-defined reset vector address. The following
sources can generate a reset:
•
Power-on reset (POR) circuit
•
RESET pin
•
Computer operating properly (COP) watchdog
•
Illegal address
ILLEGAL ADDRESS
COP WATCHDOG
VDD
POWER-ON RESET
S
D
RESET PIN
INTERNAL CLOCK
Q
RST
TO CPU AND
PERIPHERAL
MODULES
CK
RESET
LATCH
Figure 5-1. Reset Sources
5.3.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset.
NOTE:
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-tcyc (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains in the reset condition until all
reset sources are inactive.
Technical Data
64
MC68HC705KJ1 — Rev. 2.0
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Resets
VDD
OSCILLATOR STABILIZATION DELAY(2)
(NOTE 1)
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE
$07FE
$07FE
$07FE
$07FE
INTERNAL
DATA BUS
$07FE
$07FF
NEW PCH
NEW PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 5-2. Power-On Reset Timing
5.3.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 tcyc generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
$07FE
$07FE
$07FE
$07FE
NEW
PCH
INTERNAL
DATA BUS
$07FF
NEW PC
NEW
PCL
NEW PC
OP
CODE
DUMMY
tRL
RESET
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 5-3. External Reset Timing
Table 5-1. External Reset Timing
Characteristic
RESET Pulse Width
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Symbol
Min
Max
Unit
tRL
1.5
—
tcyc
Technical Data
Resets and Interrupts
65
Resets and Interrupts
5.3.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
5.3.4 Illegal Address Reset
An opcode fetch from an address not in RAM or EPROM generates a
reset.
5.4 Interrupts
The following sources can generate interrupts:
•
SWI instruction
•
External interrupt pins
– IRQ/VPP pin
– PA0–PA3 pins
•
Timer
– Real-time interrupt flag (RTIF)
– Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
5.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
Technical Data
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Resets and Interrupts
MOTOROLA
Resets and Interrupts
Interrupts
5.4.2 External Interrupt
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/VPP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is
cleared during the return from interrupt, the CPU can recognize the new
interrupt request. Figure 5-4 shows the IRQ/VPP pin interrupt logic.
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
IRQF
VDD
EXTERNAL
INTERRUPT
REQUEST
D IRQ Q
LATCH
CK
PA3
PA2
PA1
PA0
IRQE
CLR
PIRQ
(MOR)
RESET
IRQ VECTOR FETCH
IRQR
Figure 5-4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/VPP pin can be negative-edge triggered only or negative-edge and
low-level triggered. Port A external interrupt pins can be positive-edge
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Resets and Interrupts
67
Resets and Interrupts
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in Figure 5-5, is latched as long as any source
is holding an external interrupt pin low.
tILIL
EXT. INT. PIN
tILIH
tILIH
EXT. INT. PIN1
.
.
.
EXT. INT. PINn
IRQ
(INTERNAL)
Figure 5-5. External Interrupt Timing
Table 5-2. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(2)
—
tcyc
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
Table 5-3. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(2)
—
tcyc
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C unless otherwise noted.
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
Technical Data
68
MC68HC705KJ1 — Rev. 2.0
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Interrupts
5.4.3 Timer Interrupts
The timer can generate the following interrupt requests:
•
Real time
•
Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
5.4.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes
set while the real-time interrupt enable bit, RTIE, is also set. RTIF and
RTIE are in the timer status and control register.
5.4.3.2 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF and TOIE are in the timer status and control register.
5.4.4 Interrupt Processing
The CPU takes the following actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown in
Figure 5-6
•
Sets the I bit in the condition code register to prevent further
interrupts
•
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $07FC and $07FD (software interrupt vector)
– $07FA and $07FB (external interrupt vector)
– $07F8 and $07F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 5-6.
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Technical Data
Resets and Interrupts
69
Resets and Interrupts
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
UNSTACKING
ORDER
•
•
•
•
•
•
5
1
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
CONDITION CODE REGISTER
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 5-6. Interrupt Stacking Order
Technical Data
70
MC68HC705KJ1 — Rev. 2.0
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Interrupts
Table 5-4. Reset/Interrupt Vector Addresses
Function
Source
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-On
RESET Pin
COP Watchdog(1)
Illegal Address
None
None
1
$07FE–$07FF
Software
Interrupt
(SWI)
User Code
None
None
Same Priority
as Instruction
$07FC–$07FD
External
Interrupt
IRQ/VPP Pin
IRQE
I Bit
2
$07FA–$07FB
Timer
Interrupts
RTIF Bit
TOF Bit
RTIE Bit
TOIE Bit
I Bit
3
$07F8–$07F9
1. The COP watchdog is programmable in the mask option register.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Resets and Interrupts
71
Resets and Interrupts
FROM RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
NO
TIMER
INTERRUPT?
YES
STACK PC, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
NO
UNSTACK CCR, A, X, PC.
EXECUTE INSTRUCTION.
Figure 5-7. Interrupt Flowchart
Technical Data
72
MC68HC705KJ1 — Rev. 2.0
Resets and Interrupts
MOTOROLA
Technical Data — MC68HC705KJ1
Section 6. Low-Power Modes
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.3
Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.4
Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.1
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.1.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.4.1.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.2
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.2.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.2.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.4.3
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.3.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.3.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.4.4
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.4.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.4.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.5
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.5.1
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.4.5.2
WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.5
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.6
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
MC68HC705KJ1 — Rev. 2.0
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Technical Data
Low-Power Modes
73
Low-Power Modes
6.2 Introduction
The MCU can enter the following low-power standby modes:
•
Stop mode — The STOP instruction puts the MCU in its lowest
power-consumption mode.
•
Wait mode — The WAIT instruction puts the MCU in an
intermediate power-consumption mode.
•
Halt mode — Halt mode is identical to wait mode, except that an
oscillator stabilization delay of 1 to 4064 internal clock cycles
occurs when the MCU exits halt mode. The stop-to-wait
conversion bit, SWAIT, in the mask option register, enables halt
mode.
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
•
Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
6.3 Exiting Stop and Wait Modes
The following events bring the MCU out of stop mode and load the
program counter with the reset vector or with an interrupt vector:
Exiting Stop Mode
•
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
•
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Technical Data
74
MC68HC705KJ1 — Rev. 2.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Effects of Stop and Wait Modes
Exiting Wait Mode
•
External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
•
External interrupt — A high-to-low transition on the IRQ/VPP pin or
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
•
COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
•
Timer interrupt — Real-time interrupt requests and timer overflow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
6.4 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the following effects on MCU
modules.
6.4.1 Clock Generation
Effects of STOP and WAIT on clock generation are discussed here.
6.4.1.1 STOP
The STOP instruction disables the internal oscillator, stopping the CPU
clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral clocks
begin running after the oscillator stabilization delay.
NOTE:
The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Low-Power Modes
75
Low-Power Modes
6.4.1.2 WAIT
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral clocks
immediately begin running.
6.4.2 CPU
Effects of STOP and WAIT on the CPU are discussed here.
6.4.2.1 STOP
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
6.4.2.2 WAIT
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
•
Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
Technical Data
76
MC68HC705KJ1 — Rev. 2.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Effects of Stop and Wait Modes
6.4.3 COP Watchdog
Effects of STOP and WAIT on the COP watchdog are discussed here.
6.4.3.1 STOP
The STOP instruction:
NOTE:
•
Clears the COP watchdog counter
•
Disables the COP watchdog clock
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE:
Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
After exit from stop mode by reset:
•
The COP watchdog counter immediately begins counting from
$0000.
•
The COP watchdog counter is cleared at the end of the oscillator
stabilization delay and begins counting from $0000 again.
6.4.3.2 WAIT
The WAIT instruction has no effect on the COP watchdog.
NOTE:
To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Low-Power Modes
77
Low-Power Modes
6.4.4 Timer
Effects of STOP and WAIT on the timer are discussed here.
6.4.4.1 STOP
The STOP instruction:
•
Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and
control register, disabling timer interrupt requests and removing
any pending timer interrupt requests
•
Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately
resumes counting from the last value before the STOP instruction and
continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization
delay, the timer resumes operation from its reset state.
6.4.4.2 WAIT
The WAIT instruction has no effect on the timer.
6.4.5 EPROM/OTPROM
Effects of STOP and WAIT on the EPROM/OTPROM are discussed
here.
6.4.5.1 STOP
The STOP instruction during EPROM programming clears the EPGM bit
in the EPROM programming register, removing the programming
voltage from the EPROM.
6.4.5.2 WAIT
The WAIT instruction has no effect on EPROM/OTPROM operation.
Technical Data
78
MC68HC705KJ1 — Rev. 2.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Data-Retention Mode
6.5 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU
register contents at VDD voltages as low as 2.0 Vdc. The data-retention
feature allows the MCU to remain in a low power-consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
6.6 Timing
OSC
(NOTE 1)
tRL
RESET
IRQ/VPP
(NOTE 2)
tILIH
OSCILLATOR STABILIZATION DELAY(5)
IRQ/VPP
(NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
$07FE
(NOTE 4)
$07FE
$07FE
$07FE
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
$07FE
$07FF
RESET OR INTERRUPT
VECTOR FETCH
Figure 6-1. Stop Mode Recovery Timing
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Low-Power Modes
79
Low-Power Modes
STOP
SWAIT
BIT SET?
YES
HALT
WAIT
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
TIMER CLOCK ACTIVE.
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
TIMER CLOCK ACTIVE.
NO
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR.
TURN OFF INTERNAL OSCILLATOR.
YES
EXTERNAL
RESET?
YES
EXTERNAL
RESET?
YES
NO
EXTERNAL
RESET?
NO
NO
YES
EXTERNAL
INTERRUPT?
YES
EXTERNAL
INTERRUPT?
YES
NO
EXTERNAL
INTERRUPT?
NO
NO
YES
TIMER
INTERRUPT?
TURN ON INTERNAL OSCILLATOR.
RESET STABILIZATION TIMER.
YES
COP
RESET?
NO
TIMER
INTERRUPT?
NO
NO
YES
END OF
STABILIZATION
DELAY?
YES
YES
COP
RESET?
NO
NO
TURN ON CPU CLOCK.
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-2. STOP/HALT/WAIT Flowchart
Technical Data
80
MC68HC705KJ1 — Rev. 2.0
Low-Power Modes
MOTOROLA
Technical Data — MC68HC705KJ1
Section 7. Parallel I/O Ports
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.3.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.3.4
Port LED Drive Capability. . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.3.5
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .87
7.4.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.5
I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .90
7.2 Introduction
Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit
I/O port. All the bidirectional port pins are programmable as inputs or
outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Parallel I/O Ports
81
Parallel I/O Ports
Addr.
$0000
Register Name:
Port A Data Register Read:
(PORTA)
See page 83. Write:
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Reset:
$0001
Port B Data Register Read:
(PORTB)
See page 86. Write:
Unaffected by reset
0
0
See Note
Reset:
$0004
$0005
$0010
PB2
See Note
Unaffected by reset
Data Direction Register A Read:
(DDRA)
DDRA7
See page 83. Write:
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
DDRB3
DDRB2
Reset:
0
0
Data Direction Register B Read:
(DDRB)
See page 87. Write:
0
0
Reset:
0
0
0
0
0
0
0
0
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
0
0
0
0
0
0
0
0
PDIB3
PDIB2
0
0
Port A Pulldown Register Read:
(PDRA)
See page 85. Write:
Reset:
$0011
PB3
See Note
Port B Pulldown Register Read:
(PDRB)
See page 89. Write:
Reset:
See Note
0
0
See Note
See Note
0
0
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-1. Parallel I/O Port Register Summary
Technical Data
82
MC68HC705KJ1 — Rev. 2.0
Parallel I/O Ports
MOTOROLA
Parallel I/O Ports
Port A
7.3 Port A
Port A is an 8-bit bidirectional port.
7.3.1 Port A Data Register
The port A data register contains a latch for each port A pin.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-2. Port A Data Register (PORTA)
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
7.3.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input
or an output.
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-3. Data Direction Register A (DDRA)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Parallel I/O Ports
83
Parallel I/O Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 7-4 shows the I/O logic of port A.
READ DDRA
WRITE DDRA
INTERNAL DATA BUS
DDRAx
WRITE PORTA
PAx
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
PAx
(PA0–PA3 TO
IRQ MODULE)
PDRAx
100-µA
PULLDOWN
READ PORTA
WRITE PDRA
RESET
SWPDI
Figure 7-4. Port A I/O Circuitry
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 7-1 summarizes the operation
of the port A pins.
Technical Data
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MOTOROLA
Parallel I/O Ports
Port A
Table 7-1. Port A Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1
Output
Latch
Latch
1. Writing affects the data register but does not affect input.
7.3.3 Pulldown Register A
Pulldown register A inhibits the pulldown devices on port A pins
programmed as inputs.
NOTE:
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port A pins as inputs with disabled pulldown devices.
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-5. Pulldown Register A (PDRA)
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears
PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
7.3.4 Port LED Drive Capability
All outputs can drive light-emitting diodes (LEDs). These pins can sink
approximately 10 mA of current to VSS.
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Technical Data
Parallel I/O Ports
85
Parallel I/O Ports
7.3.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1,
PA0–PA3 pins function as external interrupt pins. (See Section 9.
External Interrupt Module (IRQ).)
7.4 Port B
Port B is a 2-bit bidirectional port.
7.4.1 Port B Data Register
The port B data register contains a latch for each port B pin.
Address:
Read:
$0001
Bit 7
6
0
0
5
Write:
4
See Note
Reset:
3
2
PB3
PB2
1
Bit 0
See Note
Unaffected by reset
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for
read/write but are not available externally. Configuring them as inputs will ensure that the pulldown
devices are enabled, thus properly terminating them.
Figure 7-6. Port B Data Register (PORTB)
PB[3:2] — Port B Data Bits
These read/write bits are software programmable. Data direction of each
port B pin is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
NOTE:
PB4–PB5 and PB0–PB1 should be configured as inputs at all times.
These bits are available for read/write but are not available externally.
Configuring them as inputs will ensure that the pulldown devices are
enabled, thus properly terminating them.
Technical Data
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MOTOROLA
Parallel I/O Ports
Port B
7.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output.
Address:
Read:
$0005
Bit 7
6
0
0
0
0
5
See Notes
Write:
Reset:
4
0
3
2
DDRB3
DDRB2
0
0
0
1
Bit 0
See Note
0
0
= Unimplemented
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These bits are
available for read/write but are not available externally. Configuring them as inputs will ensure that the
pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
DDRB[3:2] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[3:2], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-8 shows the I/O logic of port B.
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Technical Data
Parallel I/O Ports
87
Parallel I/O Ports
READ DDRB
WRITE DDRB
INTERNAL DATA BUS
DDRBx
WRITE PORTB
PBx
PBx
READ PORTB
WRITE PDRB
100-µA
PULLDOWN
PDRBx
RESET
SWPDI
Figure 7-8. Port B I/O Circuitry
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 7-2 summarizes the operation
of the port B pins.
Table 7-2. Port B Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, high-impedance
Pin
Latch(1)
1
Output
Latch
Latch
1. Writing affects the data register, but does not affect input.
Technical Data
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MOTOROLA
Parallel I/O Ports
Port B
7.4.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins
programmed as inputs.
NOTE:
If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with disabled pulldown devices.
Address:
$0011
Bit 7
6
5
4
3
2
PDIB3
PDIB2
0
0
1
Bit 0
Read:
Write:
Reset:
See Note
0
0
See Note
0
0
= Unimplemented
Note:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are configured as
inputs.
Figure 7-9. Pulldown Register B (PDRB)
PDIB[3:2] — Pulldown Inhibit B Bits
PDIB[3:2] disable the port B pulldown devices. Reset clears
PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
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Technical Data
Parallel I/O Ports
89
Parallel I/O Ports
7.5 I/O Port Electrical Characteristics
Table 7-3. I/O Port DC Electrical Characteristics (VDD = 5.0 V)(1)
Symbol
Min
Typ(2)
Max
Unit
I
—
—
25
mA
Output High Voltage
(ILoad = –2.5 mA) PA4–PA7
(ILoad = –5.5 mA) PB2–PB3, PA0–PA3
VOH
VDD –0.8
VDD –0.8
—
—
—
—
V
Output Low Voltage
(ILoad = 10.0 mA) PA0–PA7, PB2–PB3
VOL
—
—
0.8
V
Input High Voltage
PA0–PA7, PB2–PB3
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
PA0–PA7, PB2–PB3
VIL
VSS
—
0.2 x VDD
V
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB2–PB3 (Without Individual
Pulldown Activated)
IIL
—
0.2
±1
µA
Input Pulldown Current
PA0–PA7, PB2–PB3 (With Individual
Pulldown Activated)
IIL
35
80
200
µA
Characteristic
Current Drain Per Pin
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C.
Technical Data
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Parallel I/O Ports
MOTOROLA
Parallel I/O Ports
I/O Port Electrical Characteristics
Table 7-4. I/O Port DC Electrical Characteristics (VDD = 3.3 V)(1)
Symbol
Min
Typ(2)
Max
Unit
I
—
—
25
mA
Output High Voltage
(ILoad = –0.8 mA) PA4–PA7
(ILoad = –1.5 mA) PA0–PA3, PB2–PB3
VOH
VDD –0.3
VDD –0.3
—
—
—
—
V
Output Low Voltage
(ILoad = 5.0 mA) PA4–PA7
(ILoad = 3.5 mA) PA0–PA3, PB2–PB3
VOL
—
—
—
—
0.5
0.5
V
Input High Voltage
PA0–PA7, PB2–PB3
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
PA0–PA7, PB2–PB3
VIL
VSS
—
0.2 x VDD
V
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB2–PB3 (Without Individual Pulldown
Activated)
IIL
—
0.1
±1
µA
Input Pulldown Current
PA0–PA7, PB2–PB3 (With Individual Pulldown
Activated)
IIL
12
30
100
µA
Characteristic
Current Drain Per Pin
1. VDD = 3.3 Vdc ± 10%, VSS= 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Parallel I/O Ports
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Parallel I/O Ports
Technical Data
92
MC68HC705KJ1 — Rev. 2.0
Parallel I/O Ports
MOTOROLA
Technical Data — MC68HC705KJ1
Section 8. Computer Operating Properly Module (COP)
8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.1
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.2
COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . .94
8.4.3
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .95
8.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.6
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.2 Introduction
The computer operating properly (COP) watchdog resets the MCU in
case of software failure. Software that is operating properly periodically
services the COP watchdog and prevents COP reset. The COP
watchdog function is programmable by the COPEN bit in the mask
option register.
8.3 Features
The computer operating properly module (COP) includes these features:
•
Protection from Runaway Software
•
Wait Mode and Halt Mode Operations
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Technical Data
Computer Operating Properly Module (COP)
93
Computer Operating Properly Module (COP)
8.4 Operation
Operation of the COP module is discussed here.
8.4.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/VPP pin
voltage is between VSS and VDD. Periodically clearing the counter starts
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
NOTE:
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
8.4.2 COP Watchdog Timeout Period
The COP watchdog timer function is implemented by dividing the output
of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. (See timer status and control register
in Section 10. Multifunction Timer Module.)
Note that the minimum COP timeout period is seven times the RTI
period. The COP is cleared asynchronously with the value in the RTI
divider; hence, the COP timeout period will vary between 7x and 8x the
RTI period.
Technical Data
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Computer Operating Properly Module (COP)
MOTOROLA
Computer Operating Properly Module (COP)
Interrupts
8.4.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0 (see Figure 8-1).
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/VPP pin voltage.
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
8.5 Interrupts
The COP watchdog does not generate interrupts.
8.6 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
Address:
$07F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
COPC
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 8-1. COP Register (COPR)
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
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Technical Data
Computer Operating Properly Module (COP)
95
Computer Operating Properly Module (COP)
8.7 Low-Power Modes
The STOP and WAIT instructions have the following effects on the COP
watchdog.
8.7.1 Stop Mode
The STOP instruction clears the COP watchdog counter and disables
the clock to the COP watchdog.
NOTE:
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
Upon exit from stop mode by external reset:
•
The counter begins counting from $0000.
•
The counter is cleared again after the oscillator stabilization delay
and begins counting from $0000 again.
Upon exit from stop mode by external interrupt:
NOTE:
•
The counter begins counting from $0000.
•
The counter is not cleared again after the oscillator stabilization
delay and continues counting throughout the oscillator
stabilization delay.
Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
8.7.2 Wait Mode
The WAIT instruction has no effect on the COP watchdog.
NOTE:
To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
Technical Data
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Computer Operating Properly Module (COP)
MOTOROLA
Technical Data — MC68HC705KJ1
Section 9. External Interrupt Module (IRQ)
9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
9.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
9.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
9.4.1
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
9.4.2
Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . .101
9.5
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .102
9.6
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
9.2 Introduction
The external interrupt (IRQ) module provides asynchronous external
interrupts to the CPU. The following sources can generate external
interrupts:
•
IRQ/VPP pin
•
PA0–PA3 pins
9.3 Features
The external interrupt module (IRQ) includes these features:
•
Dedicated External Interrupt Pin (IRQ/VPP)
•
Selectable Interrupt on Four Input/Output (I/O) Pins (PA0–PA3)
•
Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity
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Technical Data
External Interrupt Module (IRQ)
97
External Interrupt Module (IRQ)
9.4 Operation
The interrupt request/programming voltage pin (IRQ/VPP) and port A
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single OR’ing function to be latched by the
IRQ latch. Figure 9-1 shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If
the IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
IRQ status and control register. If the I bit is clear and the IRQE bit is set,
the CPU then begins the interrupt sequence. This interrupt is serviced
by the interrupt service routine located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request. Figure 9-3
shows the sequence of events caused by an interrupt.
Technical Data
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External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
Operation
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
IRQF
VDD
EXTERNAL
INTERRUPT
REQUEST
D IRQ Q
LATCH
CK
PA3
PA2
PA1
PA0
IRQE
CLR
PIRQ
(MOR)
RESET
IRQ VECTOR FETCH
IRQR
Figure 9-1. IRQ Module Block Diagram
Register Name
Bit 7
Read:
IRQ Status and Control
Register (ISCR) Write:
See page 102.
Reset:
IRQE
1
6
5
4
3
2
1
Bit 0
0
0
0
IRQF
0
0
0
R
0
0
0
= Unimplemented
R
IRQR
0
0
0
0
= Reserved
Figure 9-2. IRQ Module I/O Register Summary
Table 9-1. I/O Register Address Summary
Register:
ISCR
Address:
$000A
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MOTOROLA
Technical Data
External Interrupt Module (IRQ)
99
External Interrupt Module (IRQ)
FROM RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
NO
TIMER
INTERRUPT?
YES
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
NO
YES
UNSTACK CCR, A, X, PCH, PCL.
EXECUTE INSTRUCTION.
Figure 9-3. Interrupt Flowchart
Technical Data
100
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External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
Operation
9.4.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low
level on the IRQ/VPP pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/VPP pin low.
If level-sensitive triggering is selected, the IRQ/VPP input requires an
external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not
used, it must be tied to the VDD supply.
If edge-sensitive-only triggering is selected, a falling edge on the
IRQ/VPP pin latches an external interrupt request. A subsequent
external interrupt request can be latched only after the voltage level on
the IRQ/VPP pin returns to logic 1 and then falls again to logic 0.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to improve noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed VDD.
9.4.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected
to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask
option register. This capability allows keyboard scan applications where
the transitions or levels on the I/O pins will behave the same as the
IRQ/VPP pin except for the inverted phase (logic 1, rising edge). The
active state of the IRQ/VPP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a group to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The PA0–PA3 pins can be positive-edge triggered only or positive-edge
and high-level triggered.
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Technical Data
External Interrupt Module (IRQ)
101
External Interrupt Module (IRQ)
If edge- and level-sensitive triggering is selected, a rising edge or a high
level on a PA0–PA3 pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. As long as any source is holding a PA0–PA3 pin high,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE:
The BIH and BIL instructions apply only to the level on the IRQ/VPP pin
itself and not to the output of the logic OR function with the PA0–PA3
pins. The state of the individual port A pins can be checked by reading
the appropriate port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
9.5 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. All unused bits in the ISCR read as logic
0s. The IRQF bit is cleared and the IRQE bit is set by reset.
Address:
$000A
Bit 7
Read:
6
5
4
3
2
1
Bit 0
0
0
0
IRQF
0
0
0
IRQE
Write:
Reset:
R
1
0
0
0
= Unimplemented
R
IRQR
0
0
0
0
= Reserved
Figure 9-4. IRQ Status and Control Register (ISCR)
Technical Data
102
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External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
IRQ Status and Control Register
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is
set when an external interrupt request is pending. Reset clears the
IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt requests enabled
0 = External interrupt requests disabled
The STOP and WAIT instructions set the IRQE bit so that an external
interrupt can bring the MCU out of these low-power modes. In addition,
reset sets the I bit which masks all interrupt sources.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
External Interrupt Module (IRQ)
103
External Interrupt Module (IRQ)
9.6 Timing
tILIL
IRQ/VPP PIN
tILIH
tILIH
IRQ1
.
.
.
IRQn
IRQ (INTERNAL)
Figure 9-5. External Interrupt Timing
Table 9-2. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
tILIH
1.5
—
tcyc(2)
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered)
tILIL
1.5
—
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
2. tcyc = 1/fOP; fOP = fOSC/2.
3. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
Table 9-3. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
tILIH
1.5
—
tcyc(2)
IRQ Interrupt Pulse Width
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered)
tILIL
1.5
—
tcyc
PA0–PA3 Interrupt Pulse Width High
(Edge- and Level-Triggered)
tILIH
1.5
Note(3)
tcyc
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to + 85°C, unless otherwise noted.
2. tcyc = 1/fOP; fOP = fOSC/2.
3. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tcyc.
Technical Data
104
MC68HC705KJ1 — Rev. 2.0
External Interrupt Module (IRQ)
MOTOROLA
Technical Data — MC68HC705KJ1
Section 10. Multifunction Timer Module
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
10.4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
10.6 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
10.6.1 Timer Status and Control Register . . . . . . . . . . . . . . . . . . .108
10.6.2 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .110
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
10.7.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
10.7.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
10.2 Introduction
The multifunction timer provides a timing reference with programmable
real-time interrupt capability. Figure 10-1 shows the timer organization.
10.3 Features
Features of the multifunction timer include:
•
Timer Overflow
•
Four Selectable Interrupt Rates
•
Computer Operating Properly (COP) Watchdog Timer
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Multifunction Timer Module
105
Multifunction Timer Module
RESET
OVERFLOW
÷ 4
TIMER COUNTER REGISTER
BITS [0:7] OF 15-STAGE
RIPPLE COUNTER
INTERNAL CLOCK
(XTAL ÷ 2)
INTERNAL DATA BUS
RESET
RTIFR
TOFR
RTIE
TOIE
RTIF
TOF
INTERRUPT
REQUEST
RT0
RT1
TIMER STATUS/CONTROL REGISTER
RESET
CLEAR COP TIMER
RTI RATE SELECT
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
BITS [8:14] OF 15-STAGE RIPPLE COUNTER
÷ 8
S
Q
COP RESET
R
RESET
Figure 10-1. Multifunction Timer Block Diagram
Technical Data
106
MC68HC705KJ1 — Rev. 2.0
Multifunction Timer Module
MOTOROLA
Multifunction Timer Module
Operation
Register Name
Bit 7
6
Read:
Timer Status and Control Register
(TSCR) Write:
See page 108.
Reset:
TOF
RTIF
0
Timer Counter Register (TCR) Read:
See page 110. Write:
Reset:
5
4
3
2
TOIE
RTIE
0
0
TMR7
TMR6
0
0
1
Bit 0
0
0
TOFR
RTIFR
RT1
RT0
0
0
0
1
1
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
0
0
0
0
0
0
= Unimplemented
Figure 10-2. I/O Register Summary
Table 10-1. I/O Register Address Summary
Register:
TSCR
TCR
Address:
$0008
$0009
10.4 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the
internal clock signal by four, provides the timing reference for the timer
functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer
overflow function at the eighth stage allows a timer interrupt every 1024
internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1
and RT0 bits in the timer status and control register at address $0008
allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock
cycles. The last four stages drive the selectable COP system. (For
information on the COP, refer to Section 8. Computer Operating
Properly Module (COP).)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Multifunction Timer Module
107
Multifunction Timer Module
10.5 Interrupts
The following timer sources can generate interrupts:
•
Timer overflow flag (TOF) — The TOF bit is set when the first eight
stages of the counter roll over from $FF to $00. The timer overflow
interrupt enable bit, TOIE, enables TOF interrupt requests.
•
Real-time interrupt flag (RTIF) — The RTIF bit is set when the
selected RTI output becomes active. The real-time interrupt
enable bit, RTIE, enables RTIF interrupt requests.
10.6 I/O Registers
The following registers control and monitor the timer operation:
•
Timer status and control register (TSCR)
•
Timer counter register (TCR)
10.6.1 Timer Status and Control Register
The read/write timer status and control register performs the following
functions:
•
Flags timer interrupts
•
Enables timer interrupts
•
Resets timer interrupt flags
•
Selects real-time interrupt rates
Address:
Read:
$0008
Bit 7
6
TOF
RTIF
5
4
TOIE
RTIE
Write:
Reset:
0
0
0
0
3
2
0
0
TOFR
RTIFR
0
0
1
Bit 0
RT1
RT0
1
1
= Unimplemented
Figure 10-3. Timer Status and Control Register (TSCR)
Technical Data
108
MC68HC705KJ1 — Rev. 2.0
Multifunction Timer Module
MOTOROLA
Multifunction Timer Module
I/O Registers
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected RTI output
becomes active. RTIF generates a real-time interrupt request if RTIE
is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing
to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as logic 0. Reset clears TOFR.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as logic 0. Reset clears RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as
shown in Table 10-2. Because the selected RTI output drives the
COP watchdog, changing the real-time interrupt rate also changes
the counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent can cause a
real-time interrupt request to be missed or an additional real-time
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Multifunction Timer Module
109
Multifunction Timer Module
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
Table 10-2. Real-Time Interrupt Rate Selection
RT1:RT0
RTI
Rate
RTI Period
(fOP =
2 MHz)
COP Timeout
Period
(–0/+1 RTI Period)
Minimum COP
Timeout Period
(fOP = 2 MHz)
0 0
fOP ÷ 214
8.2 ms
8 x RTI Period
65.5 ms
0 1
fOP
15
16.4 ms
8 x RTI Period
131.1 ms
1 0
fOP ÷ 216
32.8 ms
8 x RTI Period
262.1 ms
1 1
fOP ÷ 217
65.5 ms
8 x RTI Period
524.3 ms
÷2
10.6.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register shown in Figure 10-4.
Address:
Read:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 10-4. Timer Counter Register (TCR)
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Technical Data
110
MC68HC705KJ1 — Rev. 2.0
Multifunction Timer Module
MOTOROLA
Multifunction Timer Module
Low-Power Modes
10.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low
power-consumption standby states.
10.7.1 Stop Mode
The STOP instruction has the following effects on the timer:
•
Clears the timer counter
•
Clears interrupt flags (TOF and RTIF) and interrupt enable bits
(TOFE and RTIE) in TSCR, removing any pending timer interrupt
requests and disabling further timer interrupts
10.7.2 Wait Mode
The timer remains active after a WAIT instruction. Any enabled timer
interrupt request can bring the MCU out of wait mode.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Multifunction Timer Module
111
Multifunction Timer Module
Technical Data
112
MC68HC705KJ1 — Rev. 2.0
Multifunction Timer Module
MOTOROLA
Technical Data — MC68HC705KJ1
Section 11. Electrical Specifications
11.1 Contents
11.2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
11.3
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .115
11.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.5
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.6
5.0-V DC Electrical Characteristics
11.7
3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .118
11.8
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
11.9
Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
. . . . . . . . . . . . . . . . . . .117
11.10 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . .122
11.11 Control Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
113
Electrical Specifications
11.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. For guaranteed operating conditions, refer to 11.6 5.0-V DC
Electrical Characteristics and 11.7 3.3-V DC Electrical
Characteristics
Table 11-1. Maximum Ratings(1)
Rating
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
I
25
mA
Input Voltage
VIn
VSS – 0.3 to VDD + 0.3
V
IRQ/VPP Pin
VPP
VSS – 0.3
to 2 x VDD + 0.3
V
Storage Temperature Range
TSTG
–65 to +150
°C
Supply Voltage
Current Drain per Pin
(Excluding VDD, VSS)
1. Voltages are referenced to VSS.
Technical Data
114
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Operating Temperature Range
11.3 Operating Temperature Range
Package Type
MC68HC705KJ1C(1)P(2), CDW(3), CS(4)
Symbol
Value
(TL to TH)
Unit
TA
–40 to +85
°C
Symbol
Value
Unit
θJA
60
°C/W
1. C = extended temperature range
2. P = plastic dual in-line package (PDIP)
3. DW = small outline integrated circuit (SOIC)
4. S = ceramic DIP (Cerdip)
11.4 Thermal Characteristics
Characteristic
Thermal Resistance
MC68HC705KJ1P(1)
MC68HC705KJ1DW(2)
MC68HC705KJ1S(3)
1. P = plastic dual in-line package (PDIP)
2. DW = small outline integrated circuit (SOIC)
3. S = ceramic DIP (Cerdip)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
115
Electrical Specifications
11.5 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
T J = T A + (P D × θ JA )
(1)
where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O
PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD = -----------------------------T J + 273 °C
(2)
Solving equations (1) and (2) for K gives:
= PD x (TA + 273 C) +ΘJA x (PD)
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Technical Data
116
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Electrical Specifications
5.0-V DC Electrical Characteristics
11.6 5.0-V DC Electrical Characteristics
Characteristic(1)
Output High Voltage
(ILoad = –2.5 mA) PA4–PA7
(ILoad = –5.5 mA) PB2–PB3, PA0–PA3
Output Low Voltage(8)
(ILoad = 10.0 mA) PA0–PA7, PB2–PB3
Input High Voltage
PA0–PA7, PB2–PB3, IRQ/VPP, RESET, OSC1
Input Low Voltage
PA0–PA7, PB2–PB3, IRQ/VPP, RESET, OSC1
Supply Current (fOP = 2.1 MHz; fOSC = 4.2 MHz)
Run Mode(3)
Wait Mode(4)
Stop Mode(5)
Supply Current (fOP = 4.0 MHz; fOSC = 8.0 MHz)
Run Mode(3)
Wait Mode(4)
Stop Mode(5)
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB2–PB3 (Without Individual Pulldown Activated)
Input Pulldown Current
PA0–PA7, PB2–PB3 (With Individual Pulldown Activated)
Input Pullup Current
RESET
Input Current(6)
RESET, IRQ/VPP , OSC1
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ, OSC1, OSC2
Crystal/Ceramic Resonator Oscillator Mode
Internal Resistor
OSC1 to OSC2(7)
Symbol
Min
Typ(2)
Max
Unit
VOH
VDD –0.8
VDD –0.8
—
—
—
—
V
VOL
—
—
0.8
V
VIH
0.7 × VDD
—
VDD
VSS
—
0.2 × VDD
V
—
—
—
4.0
1.0
0.1
6.0
2.8
5.0
mA
mA
µA
—
—
—
5.2
1.1
0.1
7.0
3.3
5.0
mA
mA
µA
IIL
—
0.2
±1
IIL
35
80
200
IIL
–15
–35
–85
IIn
—
0.2
±1
COut
CIn
—
—
—
—
12
8
ROSC
1.0
2.0
3.0
VIL
IDD
IDD
V
µA
µA
µA
µA
pF
MΩ
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. Typical values at midpoint of voltage range, 25°C only
3. Run mode IDD is measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF
on all outputs; CL = 20 pF on OSC2.
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V;
VIH = VDD – 0.2 V.
6. Only input high current rated to +1 µA on RESET.
7. The ROSC value selected for RC oscillator versions of this device is unspecified.
8. Maximum current drain for all I/O pins combined should not exceed 100 mA.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
117
Electrical Specifications
11.7 3.3-V DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output High Voltage
(ILoad = –0.8 mA) PA4–PA7
(ILoad = –1.5 mA) PA0–PA3, PB2–PB3
VOH
VDD –0.3
VDD –0.3
—
—
—
—
V
Output Low Voltage
(ILoad = 5.0 mA) PA4–PA7
(ILoad = 3.5 mA) PA0–PA3, PB2–PB3
VOL
—
—
—
—
0.5
0.5
V
Input High Voltage
PA0–PA7, PB2–PB3, IRQ/VPP, RESET, OSC1
VIH
0.7 × VDD
—
VDD
Input Low Voltage
PA0–PA7, PB2–PB3, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
—
1.2
0.3
0.1
2.5
0.8
5.0
mA
mA
µA
—
—
—
1.4
0.3
0.1
3.0
1.0
5.0
mA
mA
µA
IIL
—
0.1
±1
IIL
12
30
100
IIL
–10
–25
–45
IIn
—
0.1
±1
COut
CIn
—
—
—
—
12
8
ROSC
1.0
2.0
3.0
Supply Current (fOP = 1.0 MHz; fOSC = 2.0 MHz)
Run Mode(3)
Wait Mode(4)
Stop Mode(5)
Supply Current (fOP = 2.1 MHz; fOSC = 4.2 MHz)
Run Mode(3)
Wait Mode(4)
Stop Mode(5)
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB2–PB3 (Without Individual Pulldown Activated)
Input Pulldown Current
PA0–PA7, PB2–PB3 (With Individual Pulldown Activated)
Input Pullup Current
RESET
Input Current(6)
RESET, IRQ/VPP, OSC1
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ/VPP, OSC1, OSC2
Crystal/Ceramic Resonator Oscillator Mode Internal
Resistor
OSC1 to OSC2(7)
IDD
IDD
V
µA
µA
µA
µA
pF
MΩ
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. Typical values at midpoint of voltage range, 25°C only
3. Run mode IDD is measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF
on all outputs; CL = 20 pF on OSC2.
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V;
VIH = VDD – 0.2 V.
6. Only input high current rated to +1 µA on RESET.
7. The ROSC value selected for RC oscillator versions of this device is unspecified.
Technical Data
118
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Driver Characteristics
11.8 Driver Characteristics
85°C
VDD – VOH (mV)
700
800
25°C
600
–40°C
500
400
300
200
25°C
600
500
–40°C
400
300
200
VDD = 5.0 V
100
85°C
700
VDD – VOH (mV)
800
VDD = 3.3 V
100
0
0
0
–2
–4
–6
–8
–10
0
–2
–4
IOH (mA)
–6
–8
–10
IOH (mA)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) ≤ 800 mV @ IOH = –2.5 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) ≤ 300 mV @ IOH = –0.8 mA.
Figure 11-1. PA4–PA7 Typical High-Side Driver Characteristics
800
800
25°C
600
–40°C
500
400
300
200
25°C
600
500
–40°C
400
300
200
VDD = 5.0 V
100
85°C
700
85°C
VDD – VOH (mV)
VDD – VOH (mV)
700
VDD = 3.3 V
100
0
0
0
–2
–4
–6
–8
–10
0
IOH (mA)
–2
–4
–6
–8
–10
IOH (mA)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) ≤ 800 mV @ IOH = –5.5 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) ≤ 300 mV @ IOH = –1.5 mA.
Figure 11-2. PA0–PA3 and PB2–PB3 Typical High-Side Driver Characteristics
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
119
Electrical Specifications
800
800
700
700
85°C
25°C
500
–40°C
400
25°C
600
VOL (mV)
VOL (mV)
600
85°C
300
500
–40°C
400
300
200
200
VDD = 5.0 V
100
VDD = 3.3 V
100
0
0
0
10
20
30
IOL (mA)
40
50
0
10
20
30
IOL (mA)
40
50
Notes:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 800 mV @ IOL = 10.0 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 500 mV @ IOL = 5.0 mA.
Figure 11-3. PA4–PA7 Typical Low-Side Driver Characteristics
800
800
85°C
700
25°C
600
–40°C
500
25°C
600
VOL (mV)
VOL (mV)
85°C
700
400
300
500
–40°C
400
300
200
200
VDD = 5.0 V
100
VDD = 3.3 V
100
0
0
0
10
IOL (mA)
20
30
0
10
20
30
IOL (mA)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 800 mV @ IOL = 10.0 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 500 mV @ IOL = 3.5 mA.
Figure 11-4. PA0–PA3 and PB2–PB3 Typical Low-Side Driver Characteristics
Technical Data
120
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Typical Supply Currents
11.9 Typical Supply Currents
7.0 mA
SEE NOTE 1
6.0 mA
5.5 V
SUPPLY CURRENT (IDD)
5.0 mA
SEE NOTE 2
4.0 mA
4.5 V
3.0 mA
2.0 mA
3.6 V
3.0 V
1.0 mA
0
0
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
INTERNAL OPERATING FREQUENCY (fOP)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
IDD ≤ 7.0 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, devices are specified and tested for
IDD ≤ 4.25 mA @ fOP = 2.1 MHz.
Figure 11-5. Typical Operating IDD (25°C)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
121
Electrical Specifications
SEE NOTE 1
SEE NOTE 2
700 µA
5.5 V
SUPPLY CURRENT (IDD)
600 µA
4.5 V
500 µA
400 µA
300 µA
3.6 V
3.0 V
200 µA
100 µA
0
0
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
INTERNAL OPERATING FREQUENCY (fOP)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for
IDD ≤ 3.25 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, devices are specified and tested for
IDD ≤ 1.75 mA @ fOP = 2.1 MHz.
Figure 11-6. Typical Wait Mode IDD (25°C)
11.10 EPROM Programming Characteristics
Characteristic(1)
Symbol
Min
Typ
Max
Programming Voltage
IRQ/VPP
VPP
16.0
16.5
17.0
Programming Current
IRQ/VPP
IPP
—
3.0
10.0
tEPGM
tMPGM
4
4
—
—
—
—
Programming Time
Per Array Byte
MOR
Unit
V
mA
ms
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
Technical Data
122
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Control Timing
11.11 Control Timing
Table 11-2. Control Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal Oscillator Option
External Clock Source
fOSC
—
dc
8.0
8.0
MHz
Internal Operating Frequency (fOSC ÷ 2)
Crystal Oscillator
External Clock
fOP
—
dc
4.0
4.0
MHz
Cycle Time (1 ÷ fOP)
tcyc
250
—
ns
RESET Pulse Width Low
tRL
1.5
—
tcyc
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
tILIH
1.5
—
tcyc
IRQ Interrupt Pulse Width Low
(Edge- and Level-Triggered)
tILIL
1.5
Note(2)
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered)
tIHIL
1.5
—
PA0–PA3 Interrupt Pulse Width
(Edge- and Level-Triggered)
tIHIH
1.5
Note(2)
tOH, tOL
100
—
OSC1 Pulse Width
tcyc
tcyc
tcyc
ns
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. The maximum width tILIL or tILIH should not be more than the number of cycles it takes to
execute the interrupt service routine plus 19 tcyc or the interrupt service routine will be
re-entered.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
123
Electrical Specifications
Table 11-3. Control Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal Oscillator Option
External Clock Source
fOSC
—
dc
4.2
4.2
MHz
Internal Operating Frequency (fOSC ÷ 2)
Crystal Oscillator
External Clock
fOP
—
dc
2.1
2.1
MHz
Cycle Time (1 ÷ fOP)
tcyc
476
—
ns
RESET Pulse Width Low
tRL
1.5
—
tcyc
IRQ Interrupt Pulse Width Low
(Edge-Triggered)
tILIH
1.5
—
tcyc
IRQ Interrupt Pulse Width Low
(Edge- and Level-Triggered)
tILIL
1.5
Note(2)
PA0–PA3 Interrupt Pulse Width High
(Edge-Triggered)
tIHIL
1.5
—
PA0–PA3 Interrupt Pulse Width
(Edge- and Level-Triggered)
tIHIH
1.5
Note(2)
tOH, tOL
200
—
OSC1 Pulse Width
tcyc
tcyc
tcyc
ns
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. The maximum width tILIL or tILIH should not be more than the number of cycles it takes to
execute the interrupt service routine plus 19 tcyc or the interrupt service routine will be
re-entered.
Technical Data
124
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Control Timing
tILIL
tILIH
IRQ PIN
tILIH
IRQ1
.
.
.
IRQn
IRQ (INTERNAL)
Figure 11-7. External Interrupt Timing
OSC (NOTE 1)
tRL
RESET
tILIH
IRQ (NOTE 2)
OSCILLATOR STABILIZATION DELAY(5)
IRQ (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE
(NOTE 4)
07FE
07FE
07FE
07FE
07FF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
5. 4064 tcyc or 128 tcyc, depending on the state of SOSCD bit in MOR
Figure 11-8. Stop Mode Recovery Timing
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Electrical Specifications
125
Electrical Specifications
VDD
(NOTE 1)
OSCILLATOR STABILIZATION DELAY(3)
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE
07FE
07FE
07FE
07FE
07FE
INTERNAL
DATA BUS
07FF
NEW
PCH
NEW
PCL
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
3. 4064 tcyc or 128 tcyc depending on the state of SOSCD bit in MOR
Figure 11-9. Power-On Reset Timing
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE
INTERNAL
DATA BUS
07FE
07FE
07FE
NEW
PCH
07FF
NEW
PCL
NEW PC
DUMMY
NEW PC
OP
CODE
tRL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 11-10. External Reset Timing
Technical Data
126
MC68HC705KJ1 — Rev. 2.0
Electrical Specifications
MOTOROLA
Technical Data — MC68HC705KJ1
Section 12. Mechanical Specifications
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.2.1 16-Pin PDIP — Case #648. . . . . . . . . . . . . . . . . . . . . . . . .128
12.2.2 16-Pin SOIC — Case #751G . . . . . . . . . . . . . . . . . . . . . . .128
12.2.3 16-Pin Cerdip — Case #620A . . . . . . . . . . . . . . . . . . . . . .129
12.2 Introduction
The MC68HC705J1A, the RC oscillator, and low-speed option devices
described in Appendix A. MC68HRC705KJ1 and Appendix B.
MC68HLC705KJ1 are available in these packages:
•
648 — Plastic dual in-line package (PDIP)
•
751G — Small outline integrated circuit (SOIC)
•
620A — Ceramic DIP (Cerdip) (windowed)
The following figures show the latest packages at the time of this
publication. To make sure that you have the latest package
specifications, contact one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– Email [email protected]
•
World-Wide Web (wwweb) at http://motorola.com/sps/
Follow Mfax or World-Wide Web on-line instructions to retrieve the
current mechanical specifications.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Mechanical Specifications
127
Mechanical Specifications
12.2.1 16-Pin PDIP — Case #648
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
SEATING
PLANE
–T–
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
12.2.2 16-Pin SOIC — Case #751G
-A16
9
-B-
8X
P
0.010 (0.25) M
1
DIM
A
B
C
D
F
G
J
K
M
P
R
B
M
8
J
D 16X
0.010 (0.25) M T A
S
B S
MILLIMETERS
INCHES
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05
10.55
0.25
0.75
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0°
7°
0.395
0.415
0.010
0.029
F
R
X 45
C
-TG 14X
K
SEATING
PLANE
M
Technical Data
128
MC68HC705KJ1 — Rev. 2.0
Mechanical Specifications
MOTOROLA
Mechanical Specifications
Introduction
12.2.3 16-Pin Cerdip — Case #620A
B
A
A
M
16
9
B
L
1
8
16X
0.25 (0.010)
E
M
F
C
K
T
N
SEATING
PLANE
G
16X
0.25 (0.010)
M
D
T A
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
J
T B
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
Technical Data
Mechanical Specifications
129
Mechanical Specifications
Technical Data
130
MC68HC705KJ1 — Rev. 2.0
Mechanical Specifications
MOTOROLA
Technical Data — MC68HC705KJ1
Section 13. Ordering Information
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.3
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.2 Introduction
This section contains ordering information for the available package
types.
13.3 MCU Order Numbers
Table 13-1 lists the MC order numbers.
Table 13-1. Order Numbers(1)
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
Order Number
PDIP
648
16
–40 to +85°C
MC68HC705KJ1C(2)
SOIC
751G
16
–40 to +85°C
MC68HC705KJ1CDW(3)
Cerdip
620A
16
–40 to +85°C
MC68HC705KJ1CS(4)
1. Refer to Appendix A. MC68HRC705KJ1 and Appendix B. MC68HLC705KJ1 for ordering information on optional low-speed and resistor-capacitor oscillator devices.
2. C = extended temperature range
3. DW = small outline integrated circuit (SOIC)
4. S = ceramic dual in-line package (Cerdip)
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
Ordering Information
131
Ordering Information
Technical Data
132
MC68HC705KJ1 — Rev. 2.0
Ordering Information
MOTOROLA
Technical Data — MC68HC705KJ1
Appendix A. MC68HRC705KJ1
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
A.3
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .134
A.4
Typical Internal Operating Frequency for
RC Oscillator Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.5
RC Oscillator Connections (No External Resistor) . . . . . . . . .136
A.6
Typical Internal Operating Frequency Versus Temperature
(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.7
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .138
A.2 Introduction
This appendix introduces the MC68HRC705KJ1, a resistor-capacitor
(RC) oscillator mask option version of the MC68HC705KJ1. All of the
information in MC68HC705KJ1 Technical Data applies to the
MC68HRC705KJ1 with the exceptions given in this appendix.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
MC68HRC705KJ1
133
MC68HRC705KJ1
A.3 RC Oscillator Connections
For greater cost reduction, the RC oscillator mask option allows the
configuration shown in Figure A-1 to drive the on-chip oscillator. Mount
the RC components as close as possible to the pins for startup
stabilization and to minimize output distortion.
OSC1
R
OSC2
R
OSC2
OSC1
MCU
VDD
C2
C1
VSS
Figure A-1. RC Oscillator Connections
NOTE:
The optional internal resistor is not recommended for configurations that
use the RC oscillator connections as shown in Figure A-1. For such
configurations, the oscillator internal resistor (OSCRES) bit of the mask
option register should be programmed to a logic 0.
Technical Data
134
MC68HC705KJ1 — Rev. 2.0
MC68HRC705KJ1
MOTOROLA
MC68HRC705KJ1
Typical Internal Operating Frequency for RC Oscillator Option
A.4 Typical Internal Operating Frequency for RC Oscillator Option
Figure A-2 shows typical internal operating frequencies at 25°C for the
RC oscillator option.
NOTE:
Tolerance for resistance is ± 50%. When selecting resistor size, consider
the tolerance to ensure that the resulting oscillator frequency does not
exceed the maximum operating frequency.
10
FREQUENCY
(MHz)
1
5.5 V
5.0 V
4.5 V
3.6 V
0.1
3.0 V
0.01
1
10
100
1000
10000
RESISTANCE (kΩ)
Figure A-2. Typical Internal Operating Frequency
for Various VDD at 25°C — RC Oscillator Option Only
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
MC68HRC705KJ1
135
MC68HRC705KJ1
A.5 RC Oscillator Connections (No External Resistor)
For maximum cost reduction, the RC oscillator mask connections shown
in Figure A-3 allow the on-chip oscillator to be driven with no external
components. This can be accomplished by programming the oscillator
internal resistor (OSCRES) bit in the mask option register to a logic 1.
When programming the OSCRES bit for the MC68HSR705KJ1, an
internal resistor is selected which yields typical internal oscillator
frequencies as shown in Figure A-4. The internal resistance for this
device is different than the resistance of the selectable internal resistor
on the MC68HC705KJ1 and the MC68HSC705KJ1 devices.
OSC1
R
OSC2
OSC2
OSC1
MCU
VDD
(EXTERNAL CONNECTIONS LEFT OPEN)
C2
C1
VSS
Figure A-3. RC Oscillator Connections (No External Resistor)
Technical Data
136
MC68HC705KJ1 — Rev. 2.0
MC68HRC705KJ1
MOTOROLA
MC68HRC705KJ1
Typical Internal Operating Frequency Versus Temperature (No External Resistor)
A.6 Typical Internal Operating Frequency Versus Temperature
(No External Resistor)
3.00
Frequency (MHz)
2.50
2.00
3.0 V
3.6 V
4.5 V
5.0 V
1.50
5.5 V
1.00
0.50
0.00
–50
0
50
100
150
Temperature (°C)
Figure A-4. Typical Internal Operating Frequency
Versus Temperature (OSCRES Bit = 1)
NOTE:
Due to process variations, operating voltages, and temperature
requirements, the internal resistance and tolerance are unspecified.
Typically for a given voltage and temperature, the frequency should not
vary more than ± 500 kHz. However, this data is not guaranteed. It is the
user’s responsibility to ensure that the resulting internal operating
frequency meets user’s requirements.
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
MC68HRC705KJ1
137
MC68HRC705KJ1
A.7 Package Types and Order Numbers
Table A-1. MC68HRC705KJ1 (RC Oscillator Option) Order
Numbers(1)
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
PDIP
648
16
–40 to +85°C
MC68HRC705KJ1C(2)P(3)
SOIC
751G
16
–40 to +85°C
MC68HRC705KJ1CDW(4)
Cerdip
620A
16
–40 to +85°C
MC68HRC705KJ1CS(5)
Order Number
1. Refer to Section 13. Ordering Information for standard part ordering information.
2. C = extended temperature range
3. P = plastic dual in-line package (PDIP)
4. DW = small outline integrated circuit (SOIC)
5. S = ceramic dual in-line package (Cerdip)
Technical Data
138
MC68HC705KJ1 — Rev. 2.0
MC68HRC705KJ1
MOTOROLA
Technical Data — MC68HC705KJ1
Appendix B. MC68HLC705KJ1
B.1 Contents
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .139
B.4
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .140
B.2 Introduction
This appendix introduces the MC68HLC705KJ1, a low-frequency
version of the MC68HC705KJ1 optimized for 32-kHz oscillators. All of
the information in MC68HC705KJ1 Technical Data applies to the
MC68HLC705KJ1 with the exceptions given in this appendix.
B.3 DC Electrical Characteristics
Table B-1. DC Electrical Characteristics (VDD = 5 V)
Characteristic
Supply Current (fOP = 16.0 kHz, fOSC = 32.0 kHz)
Run
Wait
Symbol
Min
Typ
Max
Unit
IDD
—
—
45
20
60
30
µA
Table B-2. DC Electrical Characteristics (VDD = 3.3 V)
Characteristic
Supply Current (fOP = 16.0 kHz, fOSC = 32.0 kHz)
Run
Wait
Symbol
Min
Typ
Max
Unit
IDD
—
—
25
10
35
15
µA
MC68HC705KJ1 — Rev. 2.0
MOTOROLA
Technical Data
MC68HLC705KJ1
139
MC68HLC705KJ1
MCU
RS
OSC1
RP
32 kHz
CL
CL
Figure B-1. Crystal Connections
NOTE:
Supply current is impacted by crystal type and external components.
Since each crystal has its own characteristics, the user should consult
the crystal manufacturer for appropriate values for external components.
B.4 Package Types and Order Numbers
Table B-3. MC68HLC705KJ1 (High Speed) Order Numbers(1)
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
PDIP
648
16
–40 to +85°C
MC68HLC705KJ1C(2)P
SOIC
751G
16
–40 to +85°C
MC68HLC705KJ1CDW(3)
Cerdip
620A
16
–40 to +85°C
MC68HLC705KJ1CS(4)
Order Number
1. Refer to Section 13. Ordering Information for standard part ordering information.
2. C = extended temperature range
3. DW = small outline integrated circuit (SOIC)
4. S = ceramic dual in-line package (Cerdip)
Technical Data
140
MC68HC705KJ1 — Rev. 2.0
MC68HLC705KJ1
MOTOROLA
MC68HC705KJ1 Rev. 2.0
Technical Data Book
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Motorola
6501 William Cannon Drive West
Mail Stop OE17
Austin, Texas 78735-8598
USA
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Attention: MMD Publications Department
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into
the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217.
1-800-441-2447 or 1-303-675-2140. Customer Focus Center, 1-800-521-6274
JAPAN: Motorola Japan Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-Ku, Tokyo,
Japan, 03-5487-8488
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate,
Tai Po, New Territories, Hong Kong, 852-26629298
Mfax™, Motorola Fax Back System: [email protected]; http://sps.motorola.com/mfax/;
TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848
HOME PAGE: http://motorola.com/sps/
MC68HC705KJ1/D