MOTOROLA MC74HC20

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC20A is identical in pinout to the LS20. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
14
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 28 FETs or 7 Equivalent Gates
1
1
2
4
5
6
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
14
1
ORDERING INFORMATION
LOGIC DIAGRAM
A1
B1
C1
D1
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Plastic
SOIC
TSSOP
Y1
Y = ABCD
A2
B2
C2
D2
9
10
12
13
PIN ASSIGNMENT
8
Y1
PIN 14 = VCC
PIN 7 = GND
PINS 3, 11 = NO CONNECTION
A1
1
14
VCC
B1
2
13
D2
NC
3
12
C2
C1
4
11
NC
D1
5
10
B2
Y1
6
9
A2
GND
7
8
Y2
FUNCTION TABLE
Output
Inputs
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
1/98
 Motorola, Inc. 1997
1
REV 0.1
A
B
C
D
Y
L
X
X
X
H
X
L
X
X
H
X
X
L
X
H
X
X
X
L
H
H
H
H
H
L
MC74HC20A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
S b l
Symbol
P
Parameter
T
C
di i
Test
Conditions
VCC
V
– 55 to
25_C
85_C
125_C
U i
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
MOTOROLA
2
2.4 mA
4.0 mA
5.2 mA
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC20A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Vin = VIH
|Iout|
20 µA
Maximum Low–Level Output
Voltage
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
– 55 to
25_C
85_C
125_C
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
1
10
40
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
S b l
Symbol
P
Parameter
VCC
V
– 55 to
25_C
85_C
125_C
U i
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
90
45
18
15
115
60
23
20
135
75
27
23
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
P
Di i i C
i
(P
)*
Power
Dissipation
Capacitance
(Per G
Gate)*
F
pF
26
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
tf
INPUT
A, B, C, OR D
90%
50%
10%
OUTPUT Y
tr
TEST POINT
VCC
DEVICE
UNDER
TEST
GND
tPLH
90%
50%
10%
tPHL
OUTPUT
CL*
* Includes all probe and jig capacitance
tTLH
tTHL
Figure 2. Test Circuit
A
B
Figure 1. Switching Waveforms
Y
C
D
EXPANDED LOGIC DIAGRAM
(1/2 OF THE DEVICE)
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HC20A
OUTLINE DIMENSIONS
14
8
1
7
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
D
SEATING
PLANE
K
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
1
P 7 PL
0.25 (0.010)
7
G
D
0.25 (0.010)
MOTOROLA
M
T
F
J
M
K
14 PL
B
S
M
R X 45°
C
SEATING
PLANE
B
M
A
S
4
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0_
10_
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0_
10_
0.015
0.039
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC20A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
A
–V–
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
5
MC74HC20A/D
MOTOROLA