MOTOROLA MC74HC158AD

SEMICONDUCTOR TECHNICAL DATA
! ! ! "
High–Performance Silicon–Gate CMOS
The MC74HC158A is identical in pinout to the LS158. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These devices route 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in inverted
form for the HC158A. A high level on the Output Enable input sets all four
Y outputs to a high level for the HC158A.
•
•
•
•
•
•
•
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
Output Drive Capability: 10 LSTTL Loads
1
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
DT SUFFIX
TSSOP PACKAGE
CASE 948F-01
16
Low Input Current: 1µA
1
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 74 FETs or 18.5 Equivalent Gates
LOGIC DIAGRAM
2
A0
5
A1
Nibble
A Inputs
14
A3
4
B0
B1
B2
3
7
6
9
10
12
Y0
Y1
Select
Output
Enable
Y3
Inputs
Outputs
Output
Enable
Select
Y0–Y3
H
L
L
X
L
H
H
A0–A3
B0–B3
Pin 16 = VCC
Pin 8 = GND
1
15
Pinout: 16–Lead Plastic Package (Top View)
Output
VCC Enable
16
15
FUNCTION TABLE
Data
Outputs
Y2
13
B3
A3
B3
Y3
A2
B2
Y2
14
13
12
11
10
9
8
GND
1
2
3
4
5
6
7
Select
A0
B0
Y0
A1
B1
Y1
X = Don’t Care
A0–A3, B0–B3 = the levels of the respective Data–Word inputs.
2/97
 Motorola, Inc. 1997
Plastic
SOIC
TSSOP
11
A2
Nibble
B Inputs
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
3–1
REV 1
MC74HC158A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 2)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
–55_C to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
MOTOROLA
3–2
2.4 mA
4.0 mA
5.2 mA
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC158A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Vin = VIH or VIL
|Iout|
20 µA
Maximum Low–Level Output
Voltage
Vin = VIH or VIL |Iout|
|Iout|
|Iout|
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
–55_C to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
S b l
Symbol
P
Parameter
VCC
V
–55_C to
25_C
85_C
125_C
U i
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
85
25
21
140
95
31
26
160
110
38
32
ns
tPLH,
tPHL
Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
100
85
25
21
140
95
31
26
160
110
38
32
ns
tPLH,
tPHL
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 4)
2.0
3.0
4.5
6.0
115
80
23
20
145
90
29
25
175
100
35
30
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
P
Power
Di
Dissipation
i i C
Capacitance
i
(P
(Per Package)*
P k
)*
35
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3
MOTOROLA
MC74HC158A
SWITCHING WAVEFORMS
tf
tr
VCC
90%
Input Aor B
tf
tr
Select
50%
10%
50%
10%
GND
tPLH
tPHL
90%
50%
50%
Output Y
10%
tTLH
tTHL
10%
tTLH
tTHL
Figure 1.
Figure 2. Y versus Select, Inverted
tf
tr
TEST
POINT
VCC
90%
Output Enable
50%
10%
GND
tPHL
tPLH
90%
OUTPUT
DEVICE
UNDER
TEST
CL*
50%
Output Y
10%
*Includes all probe and jig capacitance
tTHL
tTLH
Figure 3.
MOTOROLA
GND
tPLH
tPHL
90%
Output Y
VCC
90%
Figure 4. Test Circuit
3–4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC158A
PIN DESCRIPTIONS
The data present on these pins is in its inverted form for the
HC158A. For the Output Enable input at a high level, the outputs are at a high level for the HC158A.
INPUTS
A0–A3 (Pins 2,5,11,14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158A.
CONTROL INPUTS
B0–B3 (Pins 3,6,10,13)
Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and
the Output Enable input is at a low level. The data is presented
to the outputs in inverted form for the HC158A.
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects the
A inputs and a high level selects the B inputs.
OUTPUTS
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected data to be presented at the outputs. A high level on
this input sets all of the outputs to a high level for the HC158A.
Y0–Y3 (Pins 4,7,9,12)
Data outputs. The selected input nibble is presented at
these outputs when the Output Enable input is at a low level.
A0
2
4
B0
A1
3
5
7
B1
Y0
6
Y1
Nibble
Inputs
A2
Data
Outputs
11
9
B2
A3
10
14
12
B3
Output Enable
Select
Y2
13
Y3
15
1
Figure 5. Expanded Logic Diagram
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
MC74HC158A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
-A16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
-T-
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
-A-
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
-TSEATING
PLANE
MOTOROLA
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
3–6
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0°
10°
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
-B-
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040 0.070
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0°
10°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC158A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
DETAIL E
G
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
3–7
MC74HC158A/D
MOTOROLA