MOTOROLA MC74HC365

SEMICONDUCTOR TECHNICAL DATA
& "" $ "
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High–Performance Silicon–Gate CMOS
The MC54/74HC365 is identical in pinout to the LS365. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is a high–speed hex buffer with 3–state outputs and two
common active–low Output Enables. When either of the enables is high, the
buffer outputs are placed into high–impedance states. The HC365 has
noninverting outputs.
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 90 FETs or 22.5 Equivalent Gates
16
1
A1
A2
A3
A4
A5
1
1
OUTPUT ENABLE 1
15
OUTPUT ENABLE 2
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
1
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDT
2
3
4
5
6
7
10
9
12
11
14
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
LOGIC DIAGRAM
A0
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
13
Y0
Ceramic
Plastic
TSSOP
PIN ASSIGNMENT
OUTPUT
ENABLE 1
A0
Y1
Y2
Y3
Y4
Y5
PIN 16 = VCC
PIN 8 = GND
1
16
2
15
Y0
3
14
VCC
OUTPUT
ENABLE 2
A5
A1
4
13
Y5
Y1
5
12
A4
A2
6
11
Y4
Y2
7
10
A3
GND
8
9
Y3
FUNCTION TABLE
Inputs
Enable
2
A
Y
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
X = don’t care
Z = high impedance
10/95
 Motorola, Inc. 1995
1
REV 6
Output
Enable
1
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MC54/74HC365
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
TSSOP Package†
750
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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v
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v
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
6.0
± 0.1
± 1.0
± 1.0
VOH
Vin = VIH
VOL
Maximum Low–Level Output
Voltage
MOTOROLA
Maximum Input Leakage Current
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 µA
Vin = VIL
Iin
|Iout|
|Iout|
|Iout|
|Iout|
Vin = VCC or GND
2
6.0 mA
7.8 mA
V
µA
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC365
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
IOZ
Maximum Three–State
Leakage Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Maximum Input Capacitance
—
10
10
10
pF
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
—
15
15
15
pF
Symbol
Cin
Cout
Parameter
Unit
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Buffer)*
pF
40
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
VCC
tr
tf
OUTPUT ENABLE
VCC
90%
50%
10%
INPUT A
tPLH
GND
tPHL
tTLH
GND
tPZL
OUTPUT Y
90%
50%
10%
OUTPUT Y
50%
tPHZ
50%
High–Speed CMOS Logic Data
DL129 — Rev 6
10%
VOL
90%
VOH
HIGH
IMPEDANCE
tTHL
Figure 1.
HIGH
IMPEDANCE
50%
tPZH
OUTPUT Y
tPLZ
Figure 2.
3
MOTOROLA
MC54/74HC365
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kΩ
CL*
* Includes all probe and jig capacitance
Figure 3.
Figure 4.
LOGIC DETAIL
TO OTHERS
FIVE BUFFERS
ONE OF 6
BUFFERS
VCC
Y
INPUT A
OUTPUT ENABLE 1
OUTPUT ENABLE 2
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC365
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
N
SEATING
–
PLANE
K
E
F
M
G
D 16 PL
0.25 (0.010)
J 16 PL
0.25 (0.010)
T A
M
M
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
B
F
C
L
S
–T
–
SEATING
PLANE
K
H
High–Speed CMOS Logic Data
DL129 — Rev 6
M
M
J
G
D 16 PL
0.25 (0.010)
T B
S
S
T A
M
5
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
0.200
—
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
19.05 19.93
7.49
6.10
5.08
—
0.50
0.39
1.27 BSC
1.65
1.40
2.54 BSC
0.38
0.21
4.31
3.18
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
MOTOROLA
MC54/74HC365
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
ÉÉ
ÇÇ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
ÇÇ
ÉÉ
S
S
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
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6
*MC54/74HC365/D*
MC54/74HC365/D
High–Speed CMOS Logic Data
DL129 — Rev 6