SEMICONDUCTOR TECHNICAL DATA ' $ $ $ "#&" $ "$ !%$# %$!%$# $$ &"$ The MC74LCX543 is a high performance, non–inverting octal latching transceiver operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX543 inputs to be safely driven from 5V devices. The MC74LCX543 is suitable for memory address driving and all TTL level bus oriented transceiver applications. For data flow from A to B with the EAB LOW, the A–to–B Output Enable (OEAB) must be LOW in order to enable data to the B bus, as indicated in the Function Table. With EAB LOW, a LOW signal on the A–to–B Latch Enable (LEAB) input makes the A–to–B latches transparent; a subsequent LOW–to–HIGH transition of the LEAB signal will latch the A latches, and the outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3–State B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is symetric to that above, but uses the EBA, LEBA, and OEBA inputs. • • • • • • • • LOW–VOLTAGE CMOS OCTAL LATCHING TRANSCEIVER DW SUFFIX PLASTIC SOIC CASE 751E–04 24 1 Designed for 2.7 to 3.6V VCC Operation SD SUFFIX PLASTIC SSOP CASE 940D–03 24 5V Tolerant — Interface Capability With 5V TTL Logic 1 Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible LVCMOS Compatible DT SUFFIX PLASTIC TSSOP CASE 948H–01 24 24mA Balanced Output Sink and Source Capability 1 Near Zero Static Supply Current in All Three Logic States (10µA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500mA • ESD Performance: Human Body Model >2000V; Machine Model >200V PIN NAMES Pinout: 24–Lead Package (Top View) VCC EBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 Pins Function OExx Exx LExx A0–A7 B0–B7 Output Enable Inputs Enable Inputs Latch Enable Inputs 3–State Inputs/Outputs 3–State Inputs/Outputs EAB GND This document contains information on a new product. Specifications and information herein are subject to change without notice. 11/96 Motorola, Inc. 1996 1 REV 0.3 MC74LCX543 LOGIC DIAGRAM DETAIL A D 22 B0 Q LE D 3 A0 Q LE DETAIL A x 7 OEBA EBA 2 13 23 11 1 14 OEAB EAB LEAB LEBA FUNCTION TABLE Data Ports Inputs OEAB OEBA H H L EAB X X L L LEAB L X* X* Bn Input Input X X X Disable Outputs L L X X Transparent Data; Outputs Disabled H H l h l h Latch and Outputs Disabled Input Output L X l h Z Z Load and B Outputs Disabled H X X Z Hold; B Outputs Disabled L X L H L H Transparent A to B H X l h L H Latch and Display B Outputs Output Input L X* X* H L Operating Mode An X LEBA H H H EBA X L Z Z l h Load and A Outputs Disabled X H Z X Hold; A Outputs DIsabled X L L H L H Transparent B to A X H L H l h Latch and Display A Outputs H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable or Enable Low–to–High Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable or Enable Low–to–High Transition; X = Don’t Care; * = The latches are not internally gated with the Output Enables. Therefore, data at the A or B ports may enter the latches at any time, provided that the LExx and Exx pins are set accordingly. For ICC reasons, Do Not Float Inputs. MOTOROLA 2 LCX DATA BR1339 — REV 3 MC74LCX543 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter VCC DC Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Condition Unit –0.5 to +7.0 V –0.5 ≤ VI ≤ +7.0 V –0.5 ≤ VO ≤ +7.0 Output in 3–State V –0.5 ≤ VO ≤ VCC + 0.5 Note 1. V IIK DC Input Diode Current –50 VI < GND mA IOK DC Output Diode Current –50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range –65 to +150 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. 1. Output in HIGH or LOW State. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit 2.0 1.5 3.3 3.3 3.6 3.6 V 0 5.5 V 0 0 VCC 5.5 V HIGH Level Output Current, VCC = 3.0V – 3.6V –24 mA IOL LOW Level Output Current, VCC = 3.0V – 3.6V 24 mA IOH HIGH Level Output Current, VCC = 2.7V – 3.0V –12 mA IOL LOW Level Output Current, VCC = 2.7V – 3.0V TA Operating Free–Air Temperature ∆t/∆V Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH Operating Data Retention Only (HIGH or LOW State) (3–State) 12 mA –40 +85 °C 0 10 ns/V DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C Symbol Characteristic VIH HIGH Level Input Voltage (Note 2.) VIL LOW Level Input Voltage (Note 2.) VOH HIGH Level Output Voltage VOL LOW Level Output Voltage Condition Min 2.7V ≤ VCC ≤ 3.6V 2.0 2.7V ≤ VCC ≤ 3.6V Max V 0.8 2.7V ≤ VCC ≤ 3.6V; IOH = –100µA VCC – 0.2 VCC = 2.7V; IOH = –12mA 2.2 VCC = 3.0V; IOH = –18mA 2.4 VCC = 3.0V; IOH = –24mA 2.2 Unit V V 2.7V ≤ VCC ≤ 3.6V; IOL = 100µA 0.2 VCC = 2.7V; IOL= 12mA 0.4 VCC = 3.0V; IOL = 16mA 0.4 VCC = 3.0V; IOL = 24mA 0.55 V 2. These values of VI are used to test DC electrical characteristics only. LCX DATA BR1339 — REV 3 3 MOTOROLA MC74LCX543 DC ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to +85°C Symbol Characteristic Condition Min Max Unit II Input Leakage Current 2.7V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 5.5V ±5.0 µA IOZ 3–State Output Current 2.7 ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 5.5V; VI = VIH or V IL ±5.0 µA IOFF Power–Off Leakage Current VCC = 0V; VI or VO = 5.5V 10 µA ICC Quiescent Supply Current 2.7 ≤ VCC ≤ 3.6V; VI = GND or VCC 10 µA 2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V ±10 µA 2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V 500 µA ∆ICC Increase in ICC per Input AC CHARACTERISTICS (Note 3.; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω) Limits TA = –40°C to +85°C VCC = 3.0V to 3.6V Symbol Parameter VCC = 2.7V Waveform Min Max Min Max Unit tPLH tPHL Propagation Delay An to Bn or Bn to An 1 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 ns tPLH tPHL Propagation Delay LEBA to An or LEAB to Bn 4 1.5 1.5 8.5 8.5 1.5 1.5 9.5 9.5 ns tPZH tPZL Output Enable Time OEBA to An or OEAB to Bn 2 1.5 1.5 9.0 9.0 1.5 1.5 10.0 10.0 ns tPHZ tPLZ Output Disable Time OEBA to An or OEAB to Bn 2 1.5 1.5 7.0 7.0 1.5 1.5 7.5 7.5 ns tPZH tPZL Output Enable Time EBA to An or EAB to Bn 2 1.5 1.5 9.0 9.0 1.5 1.5 10.0 10.0 ns tPHZ tPLZ Output Disable Time EBA to An or EAB to Bn 2 1.5 1.5 7.0 7.0 1.5 1.5 7.5 7.5 ns ts Setup Time, HIGH to LOW Data to LExx 4 2.5 2.5 ns th Hold Time, HIGH to LOW Data to LExx 4 1.5 1.5 ns ts Setup Time, HIGH to LOW Data to Exx 4 2.5 2.5 ns th Hold Time, HIGH to LOW Data to Exx 4 1.5 1.5 ns tw Latch Enable or Enable Pulse Width, LOW 4 3.3 3.3 ns tOSHL tOSLH Output–to–Output Skew (Note 4.) 1.0 1.0 ns 3. These AC parameters are preliminary and may be modified prior to release. The maximum AC limits are design targets. Actual performance will be specified upon completion of characterization. 4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition VOLP Dynamic LOW Peak Voltage (Note 5.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V Min Typ 0.8 Max Unit V VOLV Dynamic LOW Valley Voltage (Note 5.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 5. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the LOW state. MOTOROLA 4 LCX DATA BR1339 — REV 3 MC74LCX543 CAPACITIVE CHARACTERISTICS Condition Typical Unit CIN Symbol Input Capacitance Parameter VCC = 3.3V, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance 10MHz, VCC = 3.3V, VI = 0V or VCC 25 pF 2.7V An or Bn 1.5V 0V tPLH, tPHL VOH Bn or An 1.5V VOL WAVEFORM 1 – A/B to B/A PROPAGATION DELAYS tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns 2.7V OExx or Exx 1.5V 1.5V 0V tPZH tPHZ VOH – 0.3V An or Bn 1.5V ≈ 0V tPZL An or Bn tPLZ ≈ 3.0V 1.5V VOL + 0.3V WAVEFORM 2 – OExx/Exx to A or B OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns Figure 1. AC Waveforms LCX DATA BR1339 — REV 3 5 MOTOROLA MC74LCX543 2.7V An or Bn 1.5V 0V tw NEGATIVE PULSE ts th 1.5V 1.5V 2.7V Exx or LExx tw 1.5V 1.5V 0V tPLH, tPHL POSITIVE PULSE VOH 1.5V 1.5V An or Bn tw 1.5V VOL WAVEFORM 3 – INPUT PULSE DEFINITION tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V WAVEFORM 4 – Enable to A or B PROPAGATION DELAYS, Enable MINIMUM PULSE WIDTH, A or B to Enable SETUP AND HOLD TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted Figure 2. AC Waveforms (continued) VCC PULSE GENERATOR R1 DUT CL RT TEST 6V OPEN GND RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V Open Collector/Drain tPLH and tPHL tPZH, tPHZ 6V GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 3. Test Circuit MOTOROLA 6 LCX DATA BR1339 — REV 3 MC74LCX543 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A – 24 13 –B – 1 P 12 PL 0.010 (0.25) M B M 12 J D 24 PL 0.010 (0.25) T A M B S DIM A B C D F G J K M P R S F R X 45° C –T – SEATING PLANE M K G 22 PL MILLIMETERS MIN MAX 15.25 15.54 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8° 0° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0° 8° 0.395 0.415 0.010 0.029 SD SUFFIX PLASTIC SSOP PACKAGE CASE 940D–03 ISSUE B 24X K REF 0.12 (0.005) M T U S V ÇÇÇÇ ÉÉÉ ÇÇÇÇ ÉÉÉ ÇÇÇÇ S K L/2 24 J 13 K1 B L J1 SECTION N–N PIN 1 IDENT 1 12 0.20 (0.008) M T U 0.25 (0.010) –U– A –V– N M S NOTES: 4 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 CONTROLLING DIMENSION: MILLIMETER. 6 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 8 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 9 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 10 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. N F DETAIL E 0.076 (0.003) –T– SEATING PLANE –W– C D G H LCX DATA BR1339 — REV 3 DETAIL E 7 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 8.07 8.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.44 0.60 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.317 0.328 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.017 0.024 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_ MOTOROLA MC74LCX543 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948H–01 ISSUE O 24X K REF 0.10 (0.004) 0.15 (0.006) T U T U M V S S S 2X 24 L/2 13 B –U– L PIN 1 IDENT. 12 1 0.15 (0.006) T U NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. S A –V– DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) –T– SEATING PLANE G D H –W– MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E N 0.25 (0.010) K ÉÉ ÇÇÇ ÇÇÇ ÉÉ K1 J1 M N F SECTION N–N DETAIL E J MOTOROLA 8 LCX DATA BR1339 — REV 3 MC74LCX543 Motorola reserves the right to make changes without further notice to any products herein. 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