MOTOROLA MCM63P631TQ8R

MOTOROLA
Order this document
by MCM63P631/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
MCM63P631
64K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P631 is a 2M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the 68K Family, PowerPC,
and Pentium microprocessors. It is organized as 64K words of 32 bits each.
This device integrates input registers, an output register, a 2–bit address counter,
and high speed SRAM onto a single monolithic circuit for reduced parts count in
cache data RAM applications. Synchronous design allows precise cycle control
with the use of an external clock (K). CMOS circuitry reduces the overall power
consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) controlled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P631 (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled
by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P631 operates from a 3.3 V power supply, all inputs and outputs
are LVTTL compatible.
TQ PACKAGE
TQFP
CASE 983A–01
• MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)
MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)
MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
8/4/97
 Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM63P631
1
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
ADSC
BURST
COUNTER
K2
2
16
64K x 32 ARRAY
CLR
ADSP
2
SA
SA1
SA0
ADDRESS
REGISTER
16
14
SGW
SW
SBa
SBb
WRITE
REGISTER
a
32
32
WRITE
REGISTER
b
4
DATA–IN
REGISTER
WRITE
REGISTER
c
DATA–OUT
REGISTER
K
SBc
WRITE
REGISTER
d
SBd
K2
SE1
SE2
SE3
G
ENABLE
REGISTER
K
ENABLE
REGISTER
DQa – DQd
ZZ
MCM63P631
2
MOTOROLA FAST SRAM
SA
SA
SE1
SE2
SBd
SBc
SBb
SBa
SE3
V DD
VSS
K
SGW
SW
G
ADSC
ADSP
ADV
SA
SA
PIN ASSIGNMENT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
78
3
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDD
VSS
DQb
DQb
DQb
DQb
VSS
VDD
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDD
VSS
DQa
DQa
DQa
DQa
VSS
VDD
DQa
DQa
NC
LBO
SA
SA
SA
SA
SA1
SA0
NC
NC
VSS
VDD
NC
NC
SA
SA
SA
SA
SA
SA
NC
NC
DQc
DQc
VDD
VSS
DQc
DQc
DQc
DQc
VSS
VDD
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDD
VSS
DQd
DQd
DQd
DQd
VSS
VDD
DQd
DQd
NC
MOTOROLA FAST SRAM
MCM63P631
3
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
85
ADSC
Input
Synchronous Address Status Controller: Active low, is used to latch a
new external address. Used to initiate a READ, WRITE or chip
deselect.
84
ADSP
Input
Synchronous Address Status Processor: Initiates READ or chip
deselect cycle (exception — chip deselect does not occur when ADSP
is asserted and SE1 is high).
83
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29
DQx
I/O
86
G
Input
Asynchronous Output Enable.
89
K
Input
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
64
ZZ
Input
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4, 11, 15, 20, 27, 41,
54, 61, 65, 70, 77, 91
VDD
Supply
Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
VSS
Supply
Ground.
1, 14, 16, 30, 38, 39,
42, 43, 50, 51, 66, 80
NC
—
MCM63P631
4
Description
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 5)
Address
Used
SE1
SE2
SE3
ADSP
ADSC
ADV
G3
DQx
Write 2, 4
Deselect
None
1
X
X
X
0
X
X
High–Z
X
Deselect
None
0
X
1
0
X
X
X
High–Z
X
Deselect
None
0
0
X
0
X
X
X
High–Z
X
Deselect
None
X
X
1
1
0
X
X
High–Z
X
Deselect
None
X
0
X
1
0
X
X
High–Z
X
Begin Read
External
0
1
0
0
X
X
X
High–Z
READ5
Begin Read
External
0
1
0
1
0
X
X
High–Z
READ5
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
Next Cycle
External
0
1
0
1
0
X
X
High–Z
WRITE
Continue Write
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This READ assumes the RAM was previously deselected.
MOTOROLA FAST SRAM
MCM63P631
5
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
G
I/O Status
Read
L
L
Data Out (DQx)
Read
L
H
High–Z
Write
L
X
High–Z
Deselected
L
X
High–Z
Sleep
H
X
High–Z
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
SW
SBa
SBb
SBc
SBd
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte a
H
L
L
H
H
H
Write Byte b
H
L
H
L
H
H
Write Byte c
H
L
H
H
L
H
Write Byte d
H
L
H
H
H
L
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
MCM63P631
6
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol
Value
Unit
VDD
– 0.5 to + 4.6
V
Vin, Vout
– 0.5 to VDD + 0.5
V
Output Current (per I/O)
Iout
± 20
mA
Package Power Dissipation
PD
1.6
W
Ambient Temperature
TA
0 to 70
°C
Die Temperature
TJ
110
°C
Tbias
– 10 to 85
°C
Tstg
– 55 to 125
°C
Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VDD
Temperature Under Bias
Storage Temperature
Notes
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
2
2
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
RθJA
40
25
°C/W
1, 2
Junction to Board (Bottom)
RθJB
17
°C/W
3
Junction to Case (Top)
RθJC
9
°C/W
4
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).
MOTOROLA FAST SRAM
MCM63P631
7
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Symbol
Min
Typ
Max
Unit
VDD
3.135
3.3
3.6
V
Input Low Voltage
VIL
– 0.5*
—
0.8
V
Input High Voltage
VIH
2.0**
—
VDD + 0.5
V
Parameter
Supply Voltage
* VIL ≥ – 1 V for t ≤ tKHKH/2.
** VIH ≤ VDD + 1 V for t ≤ tKHKH/2.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(I)
—
—
±1
µA
1, 2
Output Leakage Current (0 V ≤ Vin ≤ VDD)
Ilkg(O)
—
—
±1
µA
IDDA
—
—
—
—
—
—
—
—
TBD
275
220
200
mA
3, 4, 5
ISB2
—
—
2
mA
6, 7
IZZ
—
—
2
mA
2, 7, 8
ISB3
—
—
25
mA
6, 9
AC Supply Current (Device Selected, All Outputs Open,
Freq
q = Max, VDD = Max))
MCM63P631–117
MCM63P631–4.5
MCM P
MCM63P631–7
MCM63P631–8
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels)
Sleep Mode Supply Current (Sleep Mode, Freq = Max, VDD = Max,
All Other Inputs Static at CMOS Levels, ZZ ≥ VDD – 0.2 V)
TTL Standby (Device Deselected, Freq = 0, VDD = Max,
All Inputs Static at TTL Levels)
Clock Running (Device Deselected, Freq = Max,
VDD = Max, All Inputs
Toggling
p
gg g at CMOS Levels))
MCM63P631–117
MCM63P631–4.5
MCM P
MCM63P631–7
MCM63P631–8
ISB4
—
—
—
—
—
—
—
—
TBD
145
115
105
mA
6, 7
Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, All Inputs Static at TTL Levels)
MCM63P631–117
MCM63P631–4.5
MCM63P631–7
MCM63P631–8
ISB5
—
—
—
—
—
—
—
—
TBD
65
50
50
mA
6, 9
Output Low Voltage (IOL = 8 mA)
VOL
—
—
0.4
V
Output High Voltage (IOH = – 4 mA)
VOH
2.4
—
—
V
NOTES:
1. LBO pin has an internal pullup and will exhibit leakage currents of ± 5 µA.
2. ZZ pin has an internal pulldown and will exhibit leakage currents of ± 5 µA.
3. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V).
4. All addresses transition simultaneously low (LSB) and then high (MSB).
5. Data states are all zero.
6. Device in Deselected mode as defined by the Truth Table.
7. CMOS levels are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
8. Device in Sleep Mode as defined by the Asynchronous Truth Table.
9. TTL levels are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
3
5
pF
Input/Output Capacitance
CI/O
—
6
8
pF
MCM63P631
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
63P631–117
117 MHz
63P631–4.5
100 MHz
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Cycle Time
tKHKH
8.5
—
10
—
13.3
—
15
—
ns
Clock High Pulse Width
tKHKL
3.6
—
4
—
5.3
—
6
—
ns
Clock Low Pulse Width
tKLKH
3.6
—
4
—
5.3
—
6
—
ns
Clock Access Time
tKHQV
—
4.5
—
4.5
—
7
—
8
ns
Parameter
Output Enable to Output Valid
63P631–7
75 MHz
63P631–8
66 MHz
Notes
tGLQV
—
4.5
—
4.5
—
5
—
5
ns
Clock High to Output Active
tKHQX1
0
—
0
—
0
—
0
—
ns
5
Clock High to Output Change
tKHQX2
1.5
—
1.5
—
1.5
—
1.5
—
ns
5
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
0
—
ns
5
Output Disable to Q High–Z
tGHQZ
—
5.5
—
5.5
—
7
—
8
ns
5, 6
Clock High to Q High–Z
tKHQZ
1.5
5.5
1.5
5.5
2
7
2
8
ns
5, 6
2.5
—
2.5
—
2.5
—
2.5
—
ns
0.5
—
0.5
—
0.5
—
0.5
—
ns
Setup Times:
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
Hold Times:
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
Sleep Mode Standby
tZZS
—
2x
tKHKH
—
2x
tKHKH
—
2x
tKHKH
—
2x
tKHKH
ns
Sleep Mode Recovery
tZZREC
2x
tKHKH
—
2x
tKHKH
—
2x
tKHKH
—
2x
tKHKH
—
ns
tZZQZ
—
15
—
15
—
15
—
15
ns
Sleep Mode High to Q High–Z
NOTES:
1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.
2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. This parameter is sampled and is not 100% tested.
6. Measured at ± 200 mV from steady state.
OUTPUT
RL = 50 Ω
Z0 = 50 Ω
VT = 1.5 V
Figure 1. AC Test Load
MOTOROLA FAST SRAM
MCM63P631
9
MCM63P631
10
MOTOROLA FAST SRAM
DESELECTED
tKHQZ
Q(n–1)
B
SINGLE READ
tKHQX1
A
Q(A)
Q(B)
tKHQX2
t KHQV
tKHKL
Note: E low = SE2 high and SE3 low.
W low = SGW low and / or SW and SBx low.
DQx
G
W
E
SE1
ADV
ADSC
ADSP
SA
K
tKHKH
Q(B+2)
BURST READ
Q(B+1)
tGHQZ
Q(B+3)
BURST WRAPS AROUND
tKLKH
Q(B)
C
D(C)
ADSP, SA
SE2, SE3
IGNORED
READ/WRITE CYCLES
D(C+2)
BURST WRITE
D(C+1)
D(C+3)
tGLQX
D
SINGLE READ
Q(D)
t KHQV
tZZREC
NORMAL OPERATION
NO READS OR
WRITES ALLOWED
tZZS
tZZQZ
IDD
ZZ
DQ
G
W
E
ADV
ADDR
ADS
K
MOTOROLA FAST SRAM
NOTE: ADS low = ADSC low or ADSP low.
ADS high = both ADSC, ADSP high.
E low = SE1 low, SE2 high, SE3 low.
IZZ (max) specifications will not be met if inputs toggle.
I ZZ
IN SLEEP MODE
NO NEW READS OR
WRITES ALLOWED
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
NORMAL OPERATION
SLEEP MODE TIMING
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
MCM63P631
11
APPLICATION INFORMATION
The MCM63P631 BurstRAM is a high speed synchronous
SRAM intended for use primarily in secondary or level two
(L2) cache memory applications. L2 caches are found in a
variety of classes of computers — from the desktop personal
computer to the high–end servers and transaction processing machines. For simplicity, the majority of L2 caches
today are direct mapped and are single bank implementations. These caches tend to be designed for bus speeds in
the range of 33 to 66 MHz. At these bus rates, non–pipelined
(flow–through) BurstRAMs can be used since their access
times meet the speed requirements for a minimum–latency,
zero–wait state L2 cache interface. Latency is a measure
(time) of “dead” time the memory system exhibits as a result
of a memory request.
For those applications that demand bus operation at greater than 66 MHz or multi–bank L2 caches at 66 MHz, the pipelined (register/register) version of the 64K x 32 BurstRAM
(MCM63P631) allows the designer to maintain zero–wait
state operation. Multiple banks of BurstRAMs create additional bus loading and can cause the system to otherwise
miss its timing requirements. The access time (clock–to–valid–data) of a pipelined BurstRAM is inherently faster than a
non–pipelined device by a few nanoseconds. This does not
come without cost. The cost is latency — “dead” time.
Since most L2 caches are tied to the processor bus and
bus speeds continue to increase over time, pipelined (R/R)
BurstRAMs are the best choice in achieving zero–wait state
L2 cache performance. For cost–sensitive applications that
require zero–wait state L2 cache bus speeds of up to 75 MHz,
pipelined BurstRAMs are able to provide fast clock to valid
data times required of these high speed buses.
SLEEP MODE
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P631. It allows the system designer to place
the RAM in the lowest possible power condition by asserting
ZZ. The sleep mode timing diagram shows the different
modes of operation: Normal Operation, No READ/WRITE
MCM63P631
12
Allowed, and Sleep Mode. Each mode has its own set of
constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
times prior to sleep and t ZZREC nanoseconds after
recovering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to
sleep, initiation of either a read or write operation is not allowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to being in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep current (IZZ). All inputs are allowed to toggle — the RAM will not
be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
and Pentium–based systems, these SRAMs can be used in
other high speed L2 cache or memory applications that do
not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the
MCM63P631. The burst counter feature of the BurstRAM
can be disabled, and the SRAM can be configured to act
upon a continuous stream of addresses. See Figure 2.
CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL)
Non–Burst
Sync Non–Burst,
Pipelined SRAM
ADSP
ADSC
ADV
SE1
LBO
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
MOTOROLA FAST SRAM
K
ADDR
A
C
B
D
E
F
G
H
W
G
DQx
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
READS
D(G)
D(H)
WRITES
Figure 2. Configured as Non–Burst Pipelined Synchronous SRAM
MOTOROLA FAST SRAM
MCM63P631
13
ORDERING INFORMATION
(Order by Full Part Number)
MCM
63P631
XX
X
X
Motorola Memory Prefix
Blank = Trays, R = Tape and Reel
Part Number
Speed (117 = 117 MHz, 4.5 = 4.5 ns,
7 = 7 ns, 8 = 8 ns)
Package (TQ = TQFP)
Full Part Numbers — MCM63P631TQ117
MCM63P631TQ117R
MCM63P631TQ7
MCM63P631TQ7R
MCM63P631
14
MCM63P631TQ4.5
MCM63P631TQ4.5R
MCM63P631TQ8
MCM63P631TQ8R
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
4X
e
0.20 (0.008) H A–B D
2X 30 TIPS
e/2
0.20 (0.008) C A–B D
–D–
80
51
50
81
B
E/2
–A–
–X–
X=A, B, OR D
B
–B–
VIEW Y
E1 E
E1/2
BASE
METAL
PLATING
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
b1
31
100
1
30
D1/2
c
D/2
b
D1
D
0.13 (0.005)
2X 20 TIPS
A
q
2
0.10 (0.004) C
–H–
–C–
SEATING
PLANE
q
3
VIEW AB
S
S
q
1
0.25 (0.010)
R2
A2
A1
R1
L2
L
L1
VIEW AB
C A–B
S
D
S
GAGE PLANE
q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
L2
S
R1
R2
q
1
2
q3
q
q
MOTOROLA FAST SRAM
M
SECTION B–B
0.20 (0.008) C A–B D
0.05 (0.002)
c1
MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.22
0.33
0.09
0.20
0.09
0.16
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
–––
0.08
–––
0.08
0.20
0_
7_
0_
–––
11 _
13 _
11 _
13 _
INCHES
MIN
MAX
–––
0.063
0.002
0.006
0.053
0.057
0.009
0.015
0.009
0.013
0.004
0.008
0.004
0.006
0.866 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
0.018
0.030
0.039 REF
0.020 REF
0.008
–––
0.003
–––
0.003
0.008
0_
7_
0_
–––
11 _
13 _
11 _
13 _
MCM63P631
15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
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JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,
Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
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Mfax: [email protected] – TOUCHTONE 1–602–244–6609
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HOME PAGE: http://motorola.com/sps/
MCM63P631
16
◊
MCM63P631/D
MOTOROLA FAST
SRAM