MOTOROLA Order this document by MCM72BA32/D SEMICONDUCTOR TECHNICAL DATA 256KB and 512KB BurstRAM Secondary Cache Module for Pentium The MCM72BA32SG and MCM72BA64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67B518 or MCM67B618 BiCMOS BurstRAMs. Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with popular Pentium cache controllers with on board TAG. PD0 – PD2 are reserved for density and speed identification. • Pentium–style Burst Counter on Board • Dual Readout SIMM for Circuit Density MCM72BA32 MCM72BA64 136–LEAD DIMM CASE 1104–01 TOP VIEW 1 34 35 • Single 5 V ± 5% Power Supply • All Inputs and Outputs are TTL Compatible • Three State Outputs • Byte Parity • Byte Write Capability • Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz 68 • Decoupling Capacitors for each Fast Static RAM • High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes • I/Os are 3.3 V Compatible BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp. REV 2 5/95 Motorola, Inc. 1995 MOTOROLA FAST SRAM MCM72BA32•MCM72BA64 1 PIN ASSIGNMENT 136–LEAD DIMM TOP VIEW PD2 PD1 PD0 Cache Size Module VSS NC NC 512KB 72BA64SG66/60 VSS NC VSS 512KB 72BA64SG50 VSS VSS NC 256KB 72BA32SG66/60 VSS VSS VSS 256KB 72BA32SG50 PIN NAMES A0 – A15 . . . . . . . . . . . . . . . . . . . . . . Address Inputs K0, K1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock W0 – W7 . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Write E0, E1 . . . . . . . . . . . . . . . . . . . . . . . . Module Enable G0, G1 . . . . . . . . . . . . . . . . . Module Output Enable DQ0 – DQ63 . . . . . . . . . . Cache Data Input/Output DQP0 – DQP7 . . . . . . . . . Data Parity Input/Output ADSC . . . . . . . . . . . . . . Controller Address Status ADSP . . . . . . . . . . . . . . . Processor Address Status ADV . . . . . . . . . . . . . . . . . . . . . . . . . . Burst Advance PD0 – PD2 . . . . . . . . . . . . . . . . . . Presence Detect VCC . . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground PD0 PD1 DQ0 DQ1 VCC DQ4 DQ6 DQP0 DQ8 DQ10 VSS K0 VSS DQ14 VCC DQ16 DQ17 DQ19 DQ21 VCC DQP2 DQ24 DQ26 DQ28 VSS DQ31 DQP3 VSS W0 W2 ADSP ADV VCC W4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 VSS PD2 VCC DQ2 DQ3 DQ5 DQ7 VSS DQ9 DQ11 DQ12 VSS DQ13 DQ15 DQP1 VSS DQ18 DQ20 DQ22 DQ23 VSS DQ25 DQ27 DQ29 DQ30 VSS E0 W1 W3 G0 ADSC VSS G1 W5 W6 DQ32 DQ33 VSS DQ36 DQ38 DQ39 DQ40 VCC DQ43 DQ45 DQ46 DQP5 VSS K1 VSS DQ52 DQ53 DQ55 DQP6 VCC DQ58 DQ60 DQ62 DQP7 A0 A2 A4 A6 A8 A10 A12 A14 VSS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 W7 E1 DQ34 DQ35 DQ37 VCC DQP4 DQ41 DQ42 DQ44 VSS DQ47 DQ48 DQ49 VSS DQ50 DQ51 DQ54 DQ56 VSS DQ57 DQ59 DQ61 DQ63 VCC A1 A3 A5 A7 NC A9 A11 A13 A15* * This pin on the MCM72BA32 is a No Connect (NC) MCM72BA32•MCM72BA64 2 MOTOROLA FAST SRAM 64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM 16 A0 – A15 MCM67B618 A0 – A15 LW W0 8 ADSP ADSP DQ0 – DQ7 ADSC ADSC DQ8 ADV ADV UW DQ0 – DQ7 DQP0 W1 8 K0 K DQ9 – DQ16 G0 G DQ17 E0 E DQ8 – DQ15 DQP1 MCM67B618 A0 – A15 LW W2 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW DQ16 – DQ23 DQP2 W3 8 K DQ9 – DQ16 G DQ17 DQ24 – DQ31 DQP3 E MCM67B618 A0 – A15 LW W4 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW DQ32 – DQ39 DQP4 W5 8 K1 K DQ9 – DQ16 G1 G DQ17 E1 E DQ40 – DQ47 DQP5 MCM67B618 A0 – A15 LW W6 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW DQ48 – DQ55 DQP6 W7 8 K DQ9 – DQ16 G DQ17 DQ56 – DQ63 DQP7 E MOTOROLA FAST SRAM MCM72BA32•MCM72BA64 3 32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM A15 A0 – A14 NC 15 MCM67B518 A0 – A14 LW W0 8 ADSP ADSP DQ0 – DQ7 ADSC ADSC DQ8 ADV ADV UW DQ0 – DQ7 DQP0 W1 8 K0 K DQ9 – DQ16 G0 G DQ17 E0 E DQ8 – DQ15 DQP1 MCM67B518 A0 – A14 LW W2 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW DQ16 – DQ23 DQP2 W3 8 K DQ9 – DQ16 G DQ17 DQ24 – DQ31 DQP3 E MCM67B518 A0 – A14 LW W4 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW DQ32 – DQ39 DQP4 W5 8 K1 K DQ9 – DQ16 G1 G DQ17 E1 E DQ40 – DQ47 DQP5 MCM67B518 A0 – A14 LW W6 8 ADSP DQ0 – DQ7 ADSC DQ8 ADV UW DQ48 – DQ55 DQP6 W7 8 K DQ9 – DQ16 G DQ17 DQ56 – DQ63 DQP7 E MCM72BA32•MCM72BA64 4 MOTOROLA FAST SRAM MCM67B618 BLOCK DIAGRAM (See Note) ADV BURST LOGIC INTERNAL ADDRESS Q0 BINARY COUNTER K A0′ A0 Q1 A1′ CLR ADSC ADSP 64K × 18 MEMORY ARRAY 16 A1 2 A1 – A0 ADDRESS REGISTER A0 – A15 A2 – A15 16 18 WRITE REGISTER UW LW OUTPUT BUFFER 9 G DQ0 – DQ8 DQ9 – DQ17 9 DATA–IN REGISTERS ENABLE REGISTER E 9 9 9 9 NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW). BURST SEQUENCE TABLE (See Note) External Address A15 – A2 A1 A0 1st Burst Address A15 – A2 A1 A0 2nd Burst Address A15 – A2 A1 A0 3rd Burst Address A15 – A2 A1 A0 NOTE: The burst wraps around to its initial state upon completion. MOTOROLA FAST SRAM MCM72BA32•MCM72BA64 5 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) E ADSP ADSC ADV UW or LW K Address Used Operation H L X X X L–H N/A Deselected H X L X X L–H N/A Deselected L L X X X L–H External Address Read Cycle, Begin Burst L H L X L L–H External Address Write Cycle, Begin Burst L H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation G I/O Status Read L Data Out Read H High–Z Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 6.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This device contains circuitry that will ensure the output devices are in High–Z at power up. Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MCM72BA32•MCM72BA64 6 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC Input High Voltage VIH 4.75 5.25 V 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA DC CHARACTERISTICS AND SUPPLY CURRENTS Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Parameter Ilkg(I) — ± 1.0 µA Output Leakage Current (G = VIH) Ilkg(O) — ± 1.0 µA AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) ICCA66 ICCA60 ICCA50 — 1100 1100 1000 mA AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) ISB1 — 300 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 3.3 V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible Pentium bus cycles. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance Input Capacitance MOTOROLA FAST SRAM Symbol Typ Max Unit (A0 – A15, ADSP, ADSC, ADV) Cin 25 32 pF (DQ0 – DQ63, DQP0 – DQP7) CI/O 8 10 pF (Kx, Gx, Ex, Wx) Cin 12 15 pF MCM72BA32•MCM72BA64 7 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) (Wx refers to any or all byte write enables) MCM72BA64SG66 Parameter MCM72BA64SG60 MCM72BA64SG50 Symbol Min Max Min Max Min Max Unit Cycle Time tKHKH 15 — 16.7 — 20 — ns Clock Access Time tKHQV — 9 — 10 — 12 ns Output Enable to Output Valid tGLQV — 5 — 5 — 6 ns Clock High to Output Active tKHQX1 6 — 6 — 6 — ns Clock High to Output Change tKHQX2 3 — 3 — 3 — ns Output Enable to Output Active tGLQX 0 — 0 — 0 — ns Output Disable to Q High–Z tGHQZ 2 6 2 6 2 7 ns Clock High to Q High–Z tKHQZ — 6 — 6 — 6 ns Clock High Pulse Width tKHKL 5 — 5 — 6 — ns Clock Low Pulse Width tKLKH 5 — 5 — 6 — ns Notes 4 5 Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH 2.5 — 2.5 — 2.5 — ns 6 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX 0.5 — 0.5 — 0.5 — ns 6 NOTES: 1. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 2. All read and write cycle timings are referenced from K or G. 3. G is a don’t care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible Pentium external bus cycles. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled.Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled. AC TEST LOADS +5V 480 Ω OUTPUT OUTPUT Z0 = 50 Ω RL = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MCM72BA32•MCM72BA64 8 Figure 1B MOTOROLA FAST SRAM MOTOROLA FAST SRAM MCM72BA32•MCM72BA64 9 t EVKH t AVKH t ADSVKH t GLQX A1 SINGLE READ Q(A1) t KHQV t GLQV t KHEX t KHAX t KHKL t KLKH Q(A2) t KHQX2 t ADVVKH t WVKH A2 t ADSVKH t GHQZ t KHKH Q(A2 + 1) t KHQV t KHADVX t KHWX t KHADSX BURST READ Q(A2 + 2) Q(A2 + 3) Q(A2) (BURST WRAPS AROUND TO ITS INITIAL STATE) (ADV SUSPENDS BURST) NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address. DATA OUT G ADV E LW, UW ADDRESS ADSC ADSP K t KHADSX READ CYCLES Q(A2 + 1) Q(A2 + 2) t KHQZ MCM72BA32•MCM72BA64 10 MOTOROLA FAST SRAM DATA OUT DATA IN G ADV E LW, UW ADDRESS ADSC ADSP K BURST READ Q(An – 1) t EVKH t AVKH t ADSVKH Q(An) A1 A2 t KLKH t KHADSX SINGLE WRITE t GHQZ D(A1) t KHEX D(A2) D(A2 + 1) D(A2 + 3) ADSC STARTS NEW BURST D(A2 + 2) BURST WRITE (WITH A SUSPENDED CYCLE) D(A2 + 1) ADV SUSPENDS BURST W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST t KHAX t ADSVKH t KHKL t KHADSX t KHKH WRITE CYCLES D(A3) t DVKH t ADVVKH t WVKH A3 D(A3 + 2) NEW BURST WRITE D(A3 + 1) t KHDX t KHADVX t KHWX COMBINATION READ/WRITE CYCLE tKHKH K tADSVKH tKHADSX tKHKL tKLKH ADSP tAVKH ADDRESS tKHAX A1 A2 A3 tWVKH tKHWX LW, UW tADVVKH tKHADVX ADV G tDVKH tKHQV DATA IN tKHDX tGLQV D(A2) tKHQX1 DATA OUT tKHQX2 Q(A3) Q(A1) READ MOTOROLA FAST SRAM tGLQX tGHQZ WRITE Q(A3 + 1) Q(A3 + 2) BURST READ MCM72BA32•MCM72BA64 11 APPLICATION EXAMPLE DATA BUS DATA ADDRESS BUS ADDRESS CLOCK Pentium ADDR CLK ADDR DATA K0 K1 ADSC W MCM67B618FN9 G0 G1 ADSP ADV K CACHE CONTROL LOGIC MCM72BA64SG66 ADS CONTROL 512K Byte Burstable, Secondary Cache Using MCM72BA64SG66 with a 66 MHz Pentium Figure 2 ORDERING INFORMATION (Order by Full Part Number) 72BA32 MCM 72BA64 XX XX Motorola Memory Prefix Speed (66 = 66 MHz, 60 = 60 MHz, 50 = 50 MHz) Package (SG = Gold Pad SIMM) Part Number Full Part Numbers — MCM72BA32SG66 MCM72BA64SG66 MCM72BA32•MCM72BA64 12 MCM72BA32SG60 MCM72BA64SG60 MCM72BA32SG50 MCM72BA64SG50 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 136–LEAD DIMM MODULE CASE 1104–01 A 0.006 (0.15) M T Y X S C ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ U NOTE 4 COMPONENT AREA B -Y- Y S P NOTE 4 68 35 1 N 2X 34 R -X- 2X VIEW AA L V NOTE 5 F 2X FRONT VIEW J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND S DEFINE A DOUBLE–SIDED MODULE. 5. DIMENSION V DEFINES OPTIONAL SINGLE–SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. BACK VIEW W ÉÉ ÉÉ ÉÉ ÉÉ 2X 2X W R R T Q 0.006 (0.15) M T Y X ÇÇÇÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇ 136X M VIEW AA 136X 132X L D 0.004 (0.10) G L M SIDE VIEW COMPONENT AREA 2X 0.012 (0.30) -T- 136 103 69 102 ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ NOTE 6 T Y X K 136X H S DIM A B C D F G H J K L M N P Q R S T U V W Y INCHES MIN MAX 4.045 4.055 0.995 1.005 ––– 0.413 0.040 0.042 0.125 BSC 0.050 BSC ––– 0.010 0.046 0.054 0.100 ––– 1.650 BSC 0.075 0.085 0.400 BSC 0.125 ––– 0.123 0.127 0.245 0.255 0.157 ––– 0.064 0.060 3.784 BSC ––– 0.236 0.062 ––– 0.060 0.064 MILLIMETERS MIN MAX 102.74 103.00 25.27 25.53 ––– 10.50 1.02 1.07 3.18 BSC 1.27 BSC ––– 0.25 1.17 1.37 2.54 ––– 41.91 BSC 1.91 2.16 10.16 BSC 3.18 ––– 3.12 3.22 6.22 6.48 4.00 ––– 1.52 1.63 96.11 BSC ––– 6.00 1.57 ––– 1.52 1.63 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM72BA32•MCM72BA64 14 ◊ *MCM72BA32/D* MCM72BA32/D MOTOROLA FAST SRAM