MOTOROLA
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MCM72JG32/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
256K and 512K Pipelined
BurstRAM Sedcondary Cache
Module for Pentium
MCM72JG32
MCM72JG64
160–LEAD CARD
EDGE
CASE 1113A–01
TOP VIEW
The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high
performance, 256K/512K L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The modules are configured as 32K x 64 and
64K x 64 bits in a 160 pin card edge memory module. Each module uses four of
Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8
FSRAM for the tag RAM.
Bursts can be initiated with either address status processor (ADSP) or cache
address status (CADS). Subsequent burst addresses are generated internal to
the BurstRAM by the cache burst advance (CADV) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0, CLK1) input. Eight write enables are provided for byte write control.
PD0 – PD4 map into the Triton chip set for auto–configuration of the cache
control.
Module family pinout supports 5 V and 3.3 V components. It is recommended
that all power supplies be connected.
These cache modules are plug and pin compatible with the
MCM64AF32SG15, a 256K byte asynchronous module also designed for the
Pentium microprocessor in conjunction with Intel’s Triton chip set.
1
42
43
• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
80
• Fast Module Clock Rates: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM
9 ns for Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
• I/Os are 3.3 V Compatible on Data RAMs
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Series 20 Ω Resistors for Noise Immunity
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/95
Motorola, Inc. 1995
MOTOROLA
FAST SRAM
MCM72JG32•MCM72JG64
1
PIN ASSIGNMENT
160–PIN CARD EDGE MODULE
TOP VIEW
PRESENCE DETECT TABLE
Cache Size and
Functionality
Module
PD4
PD3
PD2
PD1
PD0
256K Async
MCM64AF32
VSS
NC
VSS
VSS
NC
512K Async
—
VSS
VSS
NC
VSS
NC
256K Burst
—
VSS
NC
VSS
NC
VSS
256K Pipe Burst
MCM72JG32
VSS
NC
VSS
NC
NC
512K Burst
—
VSS
VSS
NC
NC
VSS
512K Pipe Burst
MCM72JG64
VSS
VSS
NC
NC
NC
512K 2–Bank
Burst
—
VSS
VSS
NC
VSS
VSS
PIN NAMES
A3 – A18 . . . . . . . . . . . . . . . . . . . . . Cache Address
DQ0 – DQ63 . . . . . . . . . . . . . . . . Data Input/Output
CLK0, CLK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
CWE0 – CWE7 . . . . . . . . . . . Cache Write Enable
BWE** . . . . . . . . . . . . . . . . . . . . . Byte Write Enable
GWE** . . . . . . . . . . . . . . . . . . . Global Write Enable
TIO0 – TIO7 . . . . . . . . . . . . . . . . . Tag Input/Output
TWE . . . . . . . . . . . . . . . . . . . . . . . . Tag Write Enable
CADS . . . . . . . . . . . . . . . . . Cache Address Status
ADSP . . . . . . . . . . . . . . . Address Status Processor
CADV . . . . . . . . . . . . . . . . . . Cache Burst Advance
COE . . . . . . . . . . . . . . . . . . . . Cache Output Enable
CCS . . . . . . . . . . . . . . . . . . . . . . . Cache Chip Select
RSVD . . . . . . . . . . . . . . . Reserved for Future Use
PD0 – PD4 . . . . . . . . . . . . . . . . . . Presence Detect
VCC5 . . . . . . . . . . . . . . . . . . . . . + 5 V Power Supply
VCC3 . . . . . . . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect
NOTES:
* Signals in parentheses indicate pin descriptions for asynchronous Triton
chip set module.
** Signals in parentheses will be implemented in future burstable Triton modules.
{ NC for MCM72JG32, A18 for MCM72JG64.
MCM72JG32•MCM72JG64
2
VSS
TIO1
TIO7
TIO5
TIO3
(RSVD) NC
VCC5
(RSVD) NC
*(CAA4) CADV
VSS
COE
CWE5
CWE7
CWE1
VCC5
CWE3
*(CAB3) NC
*(CALE) NC
VSS
(RSVD) NC
A4
A6
A8
A10
VCC5
A17
VSS
A9
A14
A15
(RSVD) NC
PD0
PD2
PD4
VSS
CLK0
VSS
DQ63
VCC5
DQ61
DQ59
DQ57
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VSS
TIO0
TIO2
TIO6
TIO4
NC (RSVD)
VCC3
TWE
CADS (CAA3)*
VSS
CWE4
CWE6
CWE0
CWE2
VCC3
CCS (CAB4)*
NC (GWE)**
NC (BWE)**
VSS
A3
A7
A5
A11
A16
VCC3
NC (A18){
VSS
A12
A13
ADSP
NC (ECS1, CS)
NC (ECS2)
PD1
PD3
VSS
CLK1
VSS
DQ62
VCC3
DQ60
DQ58
DQ56
VSS
DQ55
DQ53
DQ51
DQ49
VSS
DQ47
DQ45
DQ43
VCC5
DQ41
DQ39
DQ37
VSS
DQ35
DQ33
DQ31
VCC5
DQ29
DQ27
DQ25
VSS
DQ23
DQ21
DQ19
VCC5
DQ17
DQ15
DQ13
VSS
DQ11
DQ9
DQ7
VCC5
DQ5
DQ3
DQ1
VSS
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
DQ54
DQ52
DQ50
DQ48
VSS
DQ46
DQ44
DQ42
VCC3
DQ40
DQ38
DQ36
VSS
DQ34
DQ32
DQ30
VCC3
DQ28
DQ26
DQ24
VSS
DQ22
DQ20
DQ18
VCC3
DQ16
DQ14
DQ12
VSS
DQ10
DQ8
DQ6
VCC3
DQ4
DQ2
DQ0
VSS
MOTOROLA FAST SRAM
MCM72JG32 MODULE BLOCK DIAGRAM
32K x 8
TIO0 – TIO7
DQ0 – DQ7
TWE
13
A5 – A17
W
A0 – A12
E
A18 – NC
A3 – A17
ADSP
15
G
MCM67J518
A0 – A14
ADSP
CADS
CADV
ADSC
CLK0
K
COE
G
E
CCS
A13
A14
ADV
LW
DQ0 – DQ7
8
CWE0
DQ0 – DQ7
8
CWE1
DQ8– DQ15
8
CWE2
DQ16 – DQ23
8
CWE3
DQ24– DQ31
8
CWE4
DQ32 – DQ39
8
CWE5
DQ40– DQ47
8
CWE6
DQ48 – DQ55
8
CWE7
DQ56– DQ63
DQ8
UW
DQ9 – DQ16
DQ17
MCM67J518
A0 – A14
ADSP
LW
DQ0 – DQ7
DQ8
ADSC
UW
DQ9 – DQ16
ADV
K
DQ17
G
E
MCM67J518
A0 – A14
ADSP
LW
DQ0 – DQ7
DQ8
ADSC
UW
DQ9 – DQ16
ADV
CLK1
K
DQ17
G
E
MCM67J518
A0 – A14
ADSP
ADSC
ADV
K
G
E
LW
DQ0 – DQ7
DQ8
UW
DQ9 – DQ16
DQ17
PD0 – NC
PD1 – NC
PD2
PD3 – NC
PD4
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
3
MCM72JG64 MODULE BLOCK DIAGRAM
32K x 8
TIO0 – TIO7
DQ0 – DQ7
TWE
14
A5 – A18
W
A0 – A13
E
A14
G
MCM67J618
A3 – A18
ADSP
16
A0 – A15
ADSP
CADS
CADV
ADSC
CLK0
K
COE
G
E
CCS
ADV
LW
DQ0 – DQ7
8
CWE0
DQ0 – DQ7
8
CWE1
DQ8– DQ15
8
CWE2
DQ16 – DQ23
8
CWE3
DQ23– DQ31
8
CWE4
DQ32 – DQ39
8
CWE5
DQ40– DQ47
8
CWE6
DQ48 – DQ55
8
CWE7
DQ56– DQ63
DQ8
UW
DQ9 – DQ16
DQ17
MCM67J618
A0 – A15
ADSP
LW
DQ0 – DQ7
DQ8
ADSC
UW
DQ9 – DQ16
ADV
K
DQ17
G
E
MCM67J618
A0 – A15
ADSP
LW
DQ0 – DQ7
DQ8
ADSC
UW
DQ9 – DQ16
ADV
CLK1
K
DQ17
G
E
MCM67J618
A0 – A15
ADSP
ADSC
ADV
K
G
E
LW
DQ0 – DQ7
DQ8
UW
DQ9 – DQ16
DQ17
PD0 – NC
PD1 – NC
PD2 – NC
PD3
PD4
MCM72JG32•MCM72JG64
4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations
Symbol
Type
Description
20, 21, 22, 23, 24, 28, 29,
101, 102, 103, 104, 106, 108, 109, 110
A3 – A18
Input
Address Inputs: These inputs are registered into data RAMs and must
meet setup and hold times. The tag RAM addresses are not registered.
36, 116
CLK0,
CLK1
Input
Clock: This signal registers the address, data in, and all control signals
except COE.
11, 12, 13, 14, 92, 93, 94, 96
CWE0 –
CWE7
Input
Cache Data Byte Write Enable: Active low write signal for data RAMs.
8
TWE
Input
Tag Write Enable: Active low write signal for tag RAMs.
—
BWE
Input
Byte Write Enable: To be used in future modules.
—
GWE
Input
Global Write Enable: To be used in future modules.
16
CCS
Input
Chip Select: Active low chip enable for data RAMs.
30
ADSP
Input
Address Status Processor: Initiates READ, WRITE, or chip deselect
cycle (Exception–chip deselect does not occur when ADSP is asserted
and CCS is high.
9
CADS
Input
Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
89
CADV
Input
Cache Burst Advance: Increments address count in accordance with
interleaved count style.
91
COE
Input
Cache Output Enable: Active low asynchronous input.
Low–enables output buffers (DQ pins)
High–DQx pins are high impedance.
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
DQ0 –
DQ63
I/O
Synchronous Data I/O:
Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.
2, 3, 4, 5, 82, 83, 84, 85
TIO0 –
TIO7
I/O
Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
33, 34, 112, 113, 114
PD0 –
PD4
—
Presence Detect: See Presence Detect Table
7, 15, 25, 39, 52, 60, 68, 76
VCC3
Supply
Power Supply: 3.3 V ± 5%.
87, 95, 105, 119, 132, 140, 148, 156
VCC5
Supply
Power Supply: 5.0 V ± 5%.
1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,
136, 144, 152, 160
VSS
Supply
Ground
6, 17, 18, 26, 31, 32, 86, 88, 97, 98, 100,
111
NC
—
MOTOROLA FAST SRAM
No Connection: There is no connection to the module.
MCM72JG32•MCM72JG64
5
64K x 18 BurstRAM BLOCK DIAGRAM (See Note)
ADV
BURST LOGIC
INTERNAL
A0′ ADDRESS
Q0
A0
CLK
BINARY
COUNTER
Q1
ADSC
16
64K x 18
MEMORY
ARRAY
A1′
A1
CLR
ADSP
2
A1 – A0
ADDRESS
REGISTER
A0 – A15
A2 – A15
16
18
WRITE
REGISTER
UW
LW
9
DQ9 – DQ17
9
DATA–OUT
REGISTERS
OUTPUT
BUFFER
G
DQ0 – DQ8
9
DATA–IN
REGISTERS
ENABLE
REGISTER
E
9
9
9
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of CWE and ADSC) is
performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by negating
both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write cycle in WRITE
CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and
a read or write (dependent on CWE) is performed using the new external address. Chip enable (E) is sampled only when
a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled
low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap
around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
64K x 18 BURST SEQUENCE TABLE (See Note)
External Address
A15 – A2
A1
A0
1st Burst Address
A15 – A2
A1
A0
2nd Burst Address
A15 – A2
A1
A0
3rd Burst Address
A15 – A2
A1
A0
NOTE: The burst wraps around to its initial state upon completion.
NOTE: The above BurstRAM Block Diagram and Burst Sequence Table apply specifically tothe 64K x 18 chip. The 32K x 18 chip is functionally
identical but has no A15.
MCM72JG32•MCM72JG64
6
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
CCS
ADSP
CADS
CADV
CWEx
CLK0/1
Address Used
Operation
H
X
L
X
X
L–H
N/A
Deselected
L
L
X
X
X
L–H
External Address
Read Cycle, Begin Burst
L
H
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
H
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
H
X
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
H
X
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
H
X
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
H
X
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except COE must meet setup and hold times for the low–to–high transition of clock (CLK0/1).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
COE
I/O Status
Read
L
Data Out
Read
H
High–Z
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Symbol
Value
Unit
VCC5
– 0.5 to + 7.0
V
Voltage Relative to VSS
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
± 30
mA
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to +70
°C
Rating
Power Supply Voltage
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Storage Temperature
MOTOROLA FAST SRAM
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
MCM72JG32•MCM72JG64
7
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
Input High Voltage
VIH
4.75
5.25
V
2.2
VCC + 0.3**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Parameter
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (COE = VIH)
Ilkg(O)
—
± 1.0
µA
TTL Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
TTL Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
3.3
V
POWER SUPPLY CURRENTS
Symbol
Max
Unit
AC Supply Current (COE = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min)
Parameter
ICCA
1300
mA
AC Standby Current (COE = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min)
ISB1
340
mA
Symbol
Max
Unit
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
(Address and Control)
Cin
28
pF
Input Capacitance
(CLK0, CLK1)
Cin
12
pF
Input/Output Capacitance
(DQ0 – DQ63)
CI/O
10
pF
MCM72JG32•MCM72JG64
8
MOTOROLA FAST SRAM
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM72JG32–66
MCM72JG64–66
Parameter
Symbol
Min
Max
Unit
Cycle Time
tKHKH
15
—
ns
Clock Access Time
tKHQV
—
7
ns
Output Enable to Output Valid
tGLQV
—
5
ns
Clock High to Output Active
tKHQX1
2
—
ns
Clock High to Output Change
tKHQX2
2
—
ns
Output Enable to Output Active
tGLQX
1
—
ns
Output Disable to Q High–Z
tGHQZ
—
6
ns
Clock High to Q High–Z
tKHQZ
2
6
ns
Clock High Pulse Width
tKHKL
5
—
ns
Clock Low Pulse Width
tKLKH
5
—
ns
Notes
5
6
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tAVKH
tADSVKH
tDVKH
tWVKH
tADVVKH
tEVKH
2.5
—
ns
7
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHADVX
tKHEX
0.5
—
ns
7
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and
ADSP high for the setup and hold times.
3. All read and write cycle timings are referenced from CLK or COE.
4. COE is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 amd Pentium external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested.
At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever ADSP or
CADS is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or CADS is low) to remain
enabled.
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
9
MCM72JG32•MCM72JG64
10
MOTOROLA FAST SRAM
DQ
COE
CADV
CCS
t KNAX
A1
t KHQX1
t KHEX
CWEx
Ax
(Address)
CADS
ADSP
t KHADSX
CLK0, CLK1
t KHQV
t KHKL
t KLKH
A2
t KHQX2
t KHADSX
Q(A1)
SINGLE READ
t EVKH
t AVKH
t ADSVKH
t KHKH
t GHQZ
t KHQV
Q(A2)
t KMWX
Q(A2+1)
t WVKH
t GLQX
t KHADVX
t ADWKH
t ADSVKH
BURST READ
Q (A2+2)
(CADV SUSPENDS BURST)
ADSP STARTS NEW BURST
A3
Q(A2+3)
DATA RAMs READ CYCLES
Q (A2)
Q (A3)
(BURST WRAPS AROUND
TO ITS INITIAL STATE)
BURST READ
Q(A3+1)
Q(A3+2)
ADSP blocked with E high,
ADDR ignored
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
11
DATA OUT
DATA IN
COE
CADV
CCS
CWEx
Ax
(Address)
CADS
ADSP
CLK0, CLK1
BURST READ
Q(An – 1)
t EVKH
t AVKH
t ADSVKH
Q(An)
A1
A2
t KLKH
t KHADSX
SINGLE WRITE
t GHQZ
D(A1)
t KHEX
D(A2)
D(A2 + 1)
D(A2 + 3)
CADS STARTS NEW BURST
D(A2 + 2)
BURST WRITE
(WITH A SUSPENDED CYCLE)
D(A2 + 1)
CADV SUSPENDS BURST
W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST
t KHAX
t ADSVKH
t KHKL
t KHADSX
t KHKH
DATA RAMs WRITE CYCLES
D(A3)
t DVKH
t ADVVKH
t WVKH
A3
D(A3 + 2)
NEW BURST WRITE
D(A3 + 1)
t KHDX
t KHADVX
t KHWX
MCM72JG32•MCM72JG64
12
MOTOROLA FAST SRAM
Q
D
COE
CADV
CWEx
Ax
(Address)
ADSP
CLK0, CLK1
t KHQX1
t AVKH
t KHAX
t ADVSKH
t KHADSX
A1
READ
t KHQV
Q(A1)
t KHKL
A2
D(A2)
WRITE
t GHQZ
t KHDX
t DVKH
t ADVKH
t KHADVX
t WVKH
t KHWX
t KHKH
t KLKH
t GLQX
A3
Q(A3 + 1)
t KHQX2
BURST READ
Q(A3)
t KHQV
DATA RAMs COMBINATION READ/WRITE CYCLES (CCS low, CADS high)
Q(A3 + 2)
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE (See Note 1 and 5)
– 15
Parameter
Symbol
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
15
—
ns
2
Address Access Time
tAVQV
—
15
ns
Output Hold from Address Change
tAXQX
4
—
ns
3, 4
NOTES:
1. CWE is high for read cycle.
2. All timings are referenced from the last valid address to the first address transition.
3. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
5. Device is continuously selected (COE = VIL).
TAG RAM READ CYCLE (See Note 5)
tAVAV
Ax (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
tAVQV
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
13
TAG RAM WRITE CYCLE (See Notes 1 and 2)
– 15
Parameter
Symbol
Min
Max
Unit
Notes
tAVAV
15
—
ns
3
Write Cycle Time
Address Setup Time
tAVWL
0
—
ns
Address Valid to End of Write
tAVWH
12
—
ns
Data Valid to End of Write
tDVWH
7
—
ns
Data Hold Time
tWHDX
0
—
ns
Write Low to Output High–Z
tWLQZ
0
7
ns
5,6,7
Write High to Output Active
tWHQX
4
—
ns
5,6,7
Write Recovery Time
tWHAX
0
—
ns
NOTES:
1. A write occurs when CWE is low.
2. If COE goes low coincident with or after CWE goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first address transition.
4. If COE ≥ VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured ±500 mV from steady–state voltage with load of Figure 2B.
7. This parameter is sampled and not 100% tested.
TAG RAM WRITE CYCLE (See Notes 1 and 2)
tAVAV
AX (ADDRESS)
tWHAX
tAVWH
tWLWH
TWE
tAVWL
tDVWH
D (DATA IN)
tWHDX
DATA VALID
tWLQZ
tWHQX
HIGH Z
HIGH Z
Q (DATA OUT)
TIMING LIMITS
AC TEST LOADS
+5 V
480 Ω
Z0 = 50 Ω
OUTPUT
OUTPUT
50 Ω
255 Ω
5 pF
VL = 1.5 V
Figure 1A
MCM72JG32•MCM72JG64
14
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
72JG32
72JG64
XX
Motorola Memory Prefix
Part Number
XX
Speed (66 = 66 MHz)
Package (SG = Gold Pad SIMM)
Full Part Numbers — MCM72JG32SG66
MCM72JG64SG66
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM72JG32•MCM72JG64
15
PACKAGE DIMENSIONS
160–LEAD
CARD EDGE MODULE
CASE 1113A–01
A
C
NOTE 4
E
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉ
COMPONENT
AREA
FULL R
B
80
–Y–
VIEW
AA
43
2X
42
AC
–X–
M
AB
NOTE 5
J
ÉÉÉ
É
ÉÉÉ
É
ÉÉÉ
É
ÉÉÉ
É
ÉÉÉ
É
160X
W
D
0.004 (0.1)
160X
L
T Y X
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS C AND V DEFINE A
DOUBLE–SIDED MODULE.
5. DIMENSION AB DEFINES OPTIONAL
SINGLE–SIDED MODULE.
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
H
160X
K
G
(N)
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
VIEW AA
123
M
SIDE VIEW
156X
160
NOTE 6
0.012 (0.3)
–T–
FRONT VIEW
R
NOTE 4
F
L
R
V
P
1
122
COMPONENT
AREA
BACK VIEW
81
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
V
W
AB
AC
INCHES
MIN
MAX
4.330
4.350
1.270
1.310
–––
0.454
0.033
0.037
2.265
2.275
0.075 BSC
0.050 BSC
–––
0.030
0.055
0.069
0.210
–––
1.955
1.965
2.155
2.165
0.110 REF
0.125
–––
0.285
0.305
0.157
–––
0.040
0.060
–––
0.262
0.072
0.076
MILLIMETERS
MIN
MAX
109.98 110.49
32.26
33.27
–––
11.53
0.84
0.94
57.53
57.79
1.91 BSC
1.27 BSC
–––
0.51
1.40
1.75
5.33
–––
49.66
49.91
54.74
54.99
2.79 REF
3.18
–––
7.24
7.75
3.99
–––
1.02
1.52
–––
6.66
1.83
1.93
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM72JG32•MCM72JG64
16
◊
*MCM72JG32/D*
MOTOROLA MCM72JG32/D
FAST SRAM