MOTOROLA MPC2106CDG66

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
512KB and 1MB BurstRAM
Secondary Cache Modules for
PowerPC PReP/CHRP Platforms
The MPC2105C and the MPC2106C are designed to provide burstable, high
performance L2 cache for the PowerPC 60x microprocessor family in conformance
with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications.
The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules
are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format.
The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3
V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus
16K x 2 for valid and dirty status bits is used.
Bursts can be initiated with the ADS signal. Subsequent burst addresses are
generated internal to the BurstRAM by the CNTEN signal.
Write cycles are internally self timed and are initiated by the rising edge of the clock
(CLKx) inputs. Eight write enables are provided for byte write control.
Presence detect pins are available for auto configuration of the cache control.
The module family pinout will support 5 V and 3.3 V components for a clear path
to lower voltage and power savings. Both power supplies must be connected.
All of these cache modules are plug and pin compatible with each other.
•
•
•
•
•
•
•
•
•
•
•
•
•
PowerPC–style Burst Counter on Chip
Flow–Through Data I/O
Plug and Pin Compatibility
Multiple Clock Pins for Reduced Loading
All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
Three State Outputs
Byte Write Capability
Fast Module Clock Rates: Up to 66 MHz
Fast SRAM Access Times: 10 ns for Tag RAM Match
9 ns for Data RAM
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
178 Pin Card Edge Module
Burndy Connector, Part Number: ELF178KSC–3Z50
Order this document
by MPC2105C/D
MPC2105C
MPC2106C
178–LEAD CARD EDGE
TOP VIEW
MPC2105C CASE 1132A–01
MPC2106C CASE 1132–01
1
24
25
47
48
89
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
10/14/97
 Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MPC2105C•MPC2106C
1
MPC2105C BLOCK DIAGRAM
VSS
BA13 – BA28
69F618CTQ
SA
SBA
ADSC
DQA
ADV
SBB
G
DQB
SE1
K
ADS0
CNTEN0
CG0
CWE0
DH0 – DH7 + DP0
CWE1
DH8 – DH15 + DP1
CLK0
69F618CTQ
SA
ADSC
ADV
G
SE1
SBA
DQA
SBB
DQB
K
SRAM TIE OFF
CWE2
DH16 – DH23 + DP2
CWE3
DH24 – DH31 + DP3
CLK0
69F618CTQ
SA
ADSC
ADV
G
SE1
SBA
DQA
SBB
DQB
K
A13 – A28
’244
CWE4
DL0 – DL7 + DP4
CWE5
DL8 – DL15 + DP5
CLK1
VDD
SE2
SW
SGW
ZZ
ADSP
69F618CTQ
SA
ADSC
ADV
G
SE1
A13 – A26
A1 – A12
TCLR
TWE
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TG
SBA
DQA
SBB
DQB
K
TAG: 16K x 12 + V + D
A0 – A13
TT1, WTD, E1
TAG0 –11
SFUNC, SG
RESET
TAH, TAG, TAD
SW
E2, PWRDN
TW
VCCQ
K
MATCH
TA, VALIDQ
WTQ
DIRTYQ
VALIDD
VCC
DIRTYD
TG
CWE6
DL16 – DL23 + DP6
CWE7
DL24 – DL31 + DP7
CLK1
VSS
VCC via 100 Ω
VDD
NC
VCC
A0
CLK3
CLK4
ALE
ADS1
CNTEN1
CG1
ADDR0
ADDR1
PD3
= NC
= NC
= NC
= NC
= NC
= NC
= NC
= NC
= NC
J3
PD2
J2
PD1
J1
PD0
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3 on SRAM.
MPC2105C•MPC2106C
2
J0
MOTOROLA FAST SRAM
MPC2106C BLOCK DIAGRAM
BA13 – BA28
’244
A12
BA12
69F618CTQ
SA
SBA
ADSC
DQA
ADV
SBB
G
DQB
SE1
K
ADS0
CNTEN0
CG0
69F618CTQ
CWE0
DH0 – DH7 + DP0
CWE1
DH8 – DH15 + DP1
CLK0
SBB
DQB
SBA
DQA
K
CWE2
DH16 – DH23 + DP2
CWE3
DH24 – DH31 + DP3
CLK1
SBB
DQB
SBA
DQA
K
CWE4
DL0 – DL7 + DP4
CWE5
DL8 – DL15 + DP5
CLK3
SBB
DQB
SBA
DQA
K
CWE6
DL16 – DL23 + DP6
CWE7
DL24 – DL31 + DP7
CLK4
SBB
DQB
SBA
DQA
K
69F618CTQ
SA
ADSC
ADV
G
SE1
SBA
DQA
SBB
DQB
K
SBA
DQA
SBB
DQB
K
SBA
DQA
SBB
DQB
K
ADS1
CNTEN1
CG1
SA
ADSC
ADV
G
SE2
69F618CTQ
69F618CTQ
SA
ADSC
ADV
G
SE1
SA
ADSC
ADV
G
SE2
69F618CTQ
69F618CTQ
SA
ADSC
ADV
G
SE1
A13 – A28
SA
ADSC
ADV
G
SE2
69F618CTQ
SA
ADSC
ADV
G
SE2
BANK B: SE1 TIED TO. VSS
BANK A: SE2 TIED TO.
VDD VIA 100 Ω.
SRAM TIE OFF
A13 – A26
A0 – A11
TCLR
TWE
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TG
TAG: 16K x 12 + V + D V
CC
A0 – A13
TT1, WTD
TAG0 –11
SFUNC, SG
RESET
TAH, TAG, TAD
SW
PWRDN
TW
VCCQ
K
MATCH
TA, VALIDQ
WTQ
DIRTYQ
VALIDD
E1
DIRTYD
E2
TG
VDD
VCC
VSS
VCC via 100 Ω
SGW
SW
ADSP
ZZ
VDD
NC
A12
VCC
E1
E2
VSS
A12
ALE
ADDR0
ADDR1
PD3
= NC
= NC
= NC
J3
PD2
J2
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3 on SRAM.
PD1
J1
PD0
J0
MOTOROLA FAST SRAM
MPC2105C•MPC2106C
3
PIN ASSIGNMENT
178–LEAD DIMM
TOP VIEW
VSS
PD1/IDSDATA
PD3
DH31
DH29
DH27
DH25
VDD
CWE3
DH23
DH21
DH18
VSS
DH16
CWE2
DH14
DH13
VCC
DH10
DH8
CEW1
DH6
VDD
DH4
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
016
107
108
109
110
111
112
113
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
PD0/IDSCLK
PD2
DH30
DH28
DH26
DH24
VDD
DP3
DH22
DH20
DH19
VSS
DH17
DP2
DH15
DH12
VCC
DH11
DH9
DP1
DH7
VDD
DH5
VSS
CLK0
VSS
DH1
CWE0
DL31
DL30
VSS
DL29
DL27
DL25
VCC
CWE7
DL23
DL21
DL19
VSS
DL17
CWE6
DL15
DL13
VSS
DL10
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
DH3
DH2
DH0
DP0
VSS
CLK1
VSS
DL28
DL26
DL24
DP7
VCC
DL22
DL20
DL18
DL16
VSS
DP6
DL14
DL12
DL11
VSS
DL9
MPC2105C•MPC2106C
4
DL8
CWE5
DL6
VDD
DL5
DL2
VSS
CLK3
VSS
CLK4
VSS
CWE4
ALE
VDD
ADDR1
RESERVED
CNTEN0
CNTEN1
A27
A24
A22
A20
VSS
A18
A16
A15
A14
VDD
A10
A8
A6
VSS
A4
A2
A1
BURSTMODE
VCC
VALIDIN
TWE
STANDBY
DIRTYOUT
VSS
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
DP5
DL7
DL4
VDD
DL3
DL1
DL0
VSS
CLK2
VSS
DP4
CG0
CG1
VDD
ADDR0
RESERVED
ADS0
ADS1
A28
A26
A25
A23
VSS
A21
A19
A17
A13
VDD
A12
A11
A9
VSS
A7
A5
A3
A0
VCC
TCLR
MATCH
TG
DIRTYIN
VSS
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
66, 67, 68, 69, 71, 72, 73,
74, 76, 77, 78, 80, 81, 82,
83, 155, 156, 157, 158,
160, 161, 162, 163, 165,
166, 167, 169, 170, 171
A0 – A28
Input
Address Inputs – (MSB:0, LSB:28).
62
ADDR0
Input
Least significant address bit when asynchronous Data RAMs are used.
151
ADDR1
Input
Next to least significant address bit when asynchronous Data RAMs are used.
64, 65
ADS0, ADS1
Input
Data RAM Address Strobe – For MPC2105C use ADS0 only. For MPC2106C
use ADS0, ADS1..
149
ALE
Input
Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
172
BURSTMODE
Input
Burstmode. 0 = Linear, 1 = Interleaved.
59, 60
CG0,
CG1
Input
Data RAM Output Enables. – For MPC2105C use CG0 only. For MPC2106C
use CG0, CG1.
30, 56, 115, 144, 146
CLK0 – CLK4
Input
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only.
For MPC2106C use all the clocks. For MPC2105C use CLK0 – CLK2 only.
153, 154
CNTEN0,
CNTEN1
Input
Data RAM Count Enables – For MPC2105C use CNTEN0 only. For
MPC2106C use CNTEN0, CNTEN1.
98, 104, 110, 118,
126, 132, 138, 148
CWE0 – CWE7
Input
Data RAM Write Enables – (MSB:0, LSB:7).
4, 5, 6, 7, 10, 11, 12, 14,
16, 17, 19, 20, 22, 24, 25,
26, 27, 93, 94, 95, 96, 99,
100, 101, 103, 105, 106,
108, 109, 111, 113, 117
DH0 – DH31
I/O
Description
High Data Bus – (MSB:0, LSB:31).
88
DIRTYIN
Input
177
DIRTYOUT
Output
Dirty input bit.
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
119, 120, 122, 123, 124, 127,
128, 129, 131, 133, 134, 136,
137, 139, 141, 142
DL0 – DL31
I/O
Low Data Bus – (MSB:0, LSB:31).
9, 15, 21, 28, 35, 42, 48, 58
DP0 – DP7
I/O
Data Parity Bits – (MSB:0, LSB:7)
86
MATCH
Output
2
PD0/IDSCLK
Input
Presence detect bit 0/EEPROM serial clock. (EEPROM option only).
Presence detect bit 1/EEPROM serial data. (EEPROM option only).
Dirty output bit.
Tag RAM active high match indication.
91
PD1/IDSDATA
I/O
3, 92
PD2, PD3
Output
63, 152
RESERVED
176
STANDBY
Input
Standby pin. Reduces standby power consumption.
85
TCLR
Input
Tag RAM clear.
87
TG
Input
Tag RAM output enable.
175
TWE
Input
Tag RAM write enable.
174
VALIDIN
Input
Tag RAM valid bit.
18, 36, 84, 107, 125, 173
VCC
Input
+ 5 V power supply. Must be connected.
8, 23, 51, 61, 75, 97,
112, 140, 150, 164
VDD
Input
+ 3.3 V power supply. Must be connected.
1, 13, 29, 31, 41, 46, 55, 57,
70, 79, 89, 90, 102, 114,
116, 121, 130, 135, 143,
145, 147, 159, 168, 178
VSS
Input
Ground.
MOTOROLA FAST SRAM
Presence detect bits.
Reserved pin.
MPC2105C•MPC2106C
5
DATA RAM MCM69F618C SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY
ADSx
CNTENx
CWEx
CLKx
Address Used
Operation
H
L
X
X
L–H
N/A
Deselected
L
L
X
L
L–H
External Address
Write Cycle, Begin Burst
L
L
X
H
L–H
External Address
Read Cycle, Begin Burst
X
H
L
L
L–H
Next Address
Write Cycle, Continue Burst
X
H
L
H
L–H
Next Address
Read Cycle, Continue Burst
X
H
H
L
L–H
Current Address
Write Cycle, Suspend Burst
X
H
H
H
L–H
Current Address
Read Cycle, Suspend Burst
NOTES:
1. X means don’t care.
2. All inputs except CG must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
CG
I/O Status
Read
L
Data Out (DQ0 – DQ8)
Read
H
High–Z
Write
X
High–Z — Data In
Deselected
X
High–Z
NOTES:
1. X means don’t care.
2. For a write operation following a read operation, CG must be high before the input data required set–up time and held high through the input
data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Data RAM
Tag
Iout
± 30
± 20
mA
MPC2105C
MPC2106C
PD
4.6
9.2
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to +70
°C
Rating
Power Supply Voltage
Voltage Relative to VSS
Output Current (per I/O)
Power Dissipation
Storage Temperature
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MPC2105C•MPC2106C
6
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, VDD = 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
VDD
4.75
3.00
5.25
3.60
V
Input High Voltage
VIH
2.2
VDD + 0.3**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
Symbol
Min
Max
Unit
Parameter
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Data RAM
Tag
Ilkg(I)
—
± 1.0
± 5.0
µA
Output Leakage Current (CG = VIH, Vout = 0 to VDD)
Data RAM
Tag
Ilkg(O)
—
± 1.0
± 5.0
µA
TTL Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
TTL Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
Symbol
Max
Unit
MPC2105C
MPC2106C
IDDA
900
1800
mA
MPC2105C
MPC2106C
ICCA
320
640
mA
MPC2105C
MPC2106C
ISB1 (VDD)
440
880
mA
MPC2105C
MPC2106C
ISB1 (VCC)
320
640
mA
Symbol
Typ
Max
Unit
Cin
—
16
8
—
15
24
12
5
pF
(MATCH, DIRTYOUT)
Cout
—
10
pF
(DH0 – DH31, DL0 – DL31)
CI/O
7
9
pF
(A0 – A11)
CI/O
—
10
pF
POWER SUPPLY CURRENTS
Parameter
AC Supply Current (CG = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns)
AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns)
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
Tag Output Capacitance
Data RAM Input/Output Capacitance
Tag Input/Output Capacitance
MOTOROLA FAST SRAM
(A13 – A28)
(Data RAM Control Pins)
(CLK0 – CLK4)
(Tag Control Pins)
MPC2105C•MPC2106C
7
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, VDD = 3.3 V ± 10% TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MPC2105C
MPC2106C
Parameter
Symbol
Min
Max
Unit
Cycle Time
tKHKH
15
—
ns
Clock Access Time
tKHQV
—
9
ns
Output Enable to Output Valid
tGLQV
—
5
ns
Clock High to Output Active
tKHQX1
6
—
ns
Clock High to Output Change
tKHQX2
3
—
ns
Output Enable to Output Active
tGLQX
0
—
ns
Output Disable to Q High–Z
tGHQZ
2
6
ns
Clock High to Q High–Z
tKHQZ
—
6
ns
Clock High Pulse Width
tKHKL
5
—
ns
Clock Low Pulse Width
tKLKH
5
—
ns
tAVKH
7.5
—
ns
5, 6
Setup Time
Address
Notes
4
Setup Times:
Address Status
Data In
Write
Address Advance
Chip Enable
tSVKH
tDVKH
tWVKH
tBAVVKH
tEVKH
2.5
—
ns
5
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHEX
0.5
—
ns
5
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. All read and write cycle timings are referenced from CLK or CG.
3. CG is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC external bus cycles.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
6. 5 ns of setup delay is incurred in address buffers.
MPC2105C•MPC2106C
8
MOTOROLA FAST SRAM
SYNCHRONOUS DATA RAM READ CYCLE
tKHKH
CLK1, CLK0
tKLKH
tKHKL
ADS0
tTSVKH
tAVKH
A(12, 13 – 26)
(See Note 1)
tKHTSX
tKHAX
A1
A2
CWE0 –
CWE7
tKHWX
tWVKH
tEVKH
tKHEX
STANDBY
tBAVKH
tKHBAX
CNTEN0
tKHQV
tGLQV
CG
tGLQX
tKHQX1
DATA OUT
Q (A1)
READ
tGHQZ
tKHQX2
Q (A2)
tKHQZ
tKHQV
Q (A2 + 1)
Q (A2 + 2)
Q (A2 + 3)
BURST READ
NOTES:
1. Cache addresses used are: 13 – 26 for MPC2105C; and 12 – 26 for MPC2106C.
2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with
A2 as the base address.
MOTOROLA FAST SRAM
MPC2105C•MPC2106C
9
SYNCHRONOUS DATA RAM WRITE CYCLE
tKHKH
CLK1, CLK0
tKLKH
tKHKL
tSVKH
tKHTSX
tAVKH
tKHAX
ADS0
tAVKH
A(12, 13 – 26)
tKHAX
A1
A2
tKHWX
tWVKH
CWE0 – CWE7
tEVKH
tKHEX
STANDBY
tBAVKH
tKHBAX
CNTEN0
tDVKH
DATA IN
D (A1)
SINGLE WRITE
tKHDX
D (A2)
D (A2 + 1)
D (A2 + 2)
D (A2 + 3)
BURST WRITE
NOTES:
1. Cache addresses used are: 13 – 26 for MPC2105C; and 12 – 26 for MPC2106C.
2. CG0 = VIH
MPC2105C•MPC2106C
10
MOTOROLA FAST SRAM
TAG RAM
RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)
TCLR
CLK
TWE
TAG0 – TAG11
DIRTYOUT
MATCH
Operation
POWER
L(3)
Reset Status
Active
—
Not Allowed
—
L
L–H
H
High–Z
L(3)
L
L–H
L
—
—
NOTES:
1. H = VIH, L = VIL, X = don‘t care, — = undefined.
2. TG is X for this table.
3. These are output states.
READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)
TG
TWE
CLK
TAG0 – TAG11
VALIDIN
DIRTYIN
DIRTYOUT
MATCH
Operation
L
H
X
Dout
—
—
Dout
Dout
Read Tag I/O
H
X
X
High–Z
—
—
—
—
Tag I/O Disable
WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)
TG
TWE
CLK
TAG0 – TAG11
VALIDIN
DIRTYIN
DIRTYOUT
MATCH
Operation
H
L
L–H
Din
—
—
—
L
Write Tag I/O
L
L
L–H
—
—
—
—
—
Not Allowed
NOTES:
1. H = VIH, L = VIL, X = don‘t care, — = undefined.
2. This table applies when RESET and PWRDN are high.
3. Dout in this case is the same as Din. The input data is written through to the outputs during the write operation.
MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)
TG
TWE
TAG0 – TAG11
VALIDIN(4)
DIRTYIN(4)
MATCH
Operation
X
X
—
—
—
Dout
Selected
L
H
Dout
—
—
L
Read Tag I/O
H
L
Din
Din
Din
L
Write Tag I/O, Status Bits
H
H
TAGin
L
—
L
Invalid Data – Dedicated Status Bits
H
H
TAGin
H
—
H
Match – Dedicated Status Bits
NOTES:
1. H = VIH, L = VIL, X = don‘t care, — = undefined.
2. M = high if TAGin equals the memory contents at the address; M = low if TAGin does not equal the contents at that address.
3. PWRDN and RESET are high for this table. GS and CLK are X.
4. This column represents the stored memory cell data for the given status bit at the selected address.
MOTOROLA FAST SRAM
MPC2105C•MPC2106C
11
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Unit
Clock Access Time
tKHQV
—
10
ns
Output Enable to Output Valid
tGLQV
—
8
ns
Output Enable to Output Active
tGLQX
0
—
ns
Output Disable to Q High–Z
tGHQZ
1
6
ns
Status Bit Hold from Address Change
tAXSX
3
—
ns
Address Access Time Status Bits
tAVSV
—
10
ns
Tag Bit Hold from Address Change
tAVQX
3
—
ns
Address Access Time Tag Bits
tAVQV
—
12
ns
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Unit
Cycle Time
tKHKH
15
—
ns
Clock High Pulse Width
tKHKL
4.5
—
ns
Clock Low Pulse Width
tKLKH
4.5
—
ns
Clock High to Output Active
tKHQX
1.5
—
ns
Setup Times
Address
Write
tAVKH
tWVKH
3
—
ns
Hold Times
Address
Write
tKHAX
tKHWX
1.5
—
ns
Status Output Hold
tKHSX
0
—
ns
Clock High to Status Bits Valid
tKHSV
—
9
ns
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag writes are synchronous.
MPC2105C•MPC2106C
12
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
MPC2105C•MPC2106C
13
DIRTYOUT
VALIDIN
DIRTYIN
A0 – A11
TG
TWE
A(12, 13,–26
(See Note 3)
CLK
t WVKH
t AVKH
t WVKH
t AVKH
VALID
t KHWX
t KHAX
t KHWX
t WVKH
t KHAX
t KHKH
t KHSV
VALID INPUT
VALID
t KHSX
t KLKH
VALID
t AXSX
t AVSV
t KHQX
(See Note 1)
t KHQV
t KHWX
TAG READ
AFTER WRITE
NOTES:
1. Transition is measured plus or minus 200 mV from steady state.
2. TCLR = High.
3. Cache addresses used are: A13 – A26 for MPC2105C, A12 – A26 for MPC2106C.
t KHKL
STATUS WRITE
TAG WRITE
(See Note 1)
t GHQZ
VALID
VALID OUTPUT
VALID
TAG RAM WRITE AND READ CYCLES (See Note 2)
t GLQX
t GLQV
VALID
VALID
OUTPUT
VALID
t AVSV
t AXSX
t AXQX
t AVQV
TAG READ
AFTER READ
VALID
VALID
OUTPUT
TAG RAM MATCH CYCLE
Tag RAM
Parameter
Symbol
Min
Max
Unit
Clock High Write to MATCH Invalid
tKHML
—
7
ns
Clock High Read to MATCH Valid
tKHMV
—
10
ns
Address Valid to MATCH Valid
tAVMV
—
10
ns
MATCH Valid Hold from Address Change
tAXMX
2
—
ns
TG Low to MATCH Invalid
tGLML
—
7
ns
TG High to MATCH Valid
tGHMX
—
8
ns
TAG RAM RESET (TCLR) CYCLE
Tag RAM
Parameter
Symbol
Min
Max
Unit
TCLR Setup Time
tSTC
4
—
ns
TCLR Hold Time
tHTC
1
—
ns
Status Bit Reset Time
tSRST
—
60
ns
Status Bit Hold from TCLR Low
tSHRS
2
—
ns
TCLR Low to MATCH Invalid
tRSML
—
10
ns
TCLR High to MATCH Valid
tRSMV
—
100
ns
TCLR Low to TAG High–Z
tRSQZ
—
10
ns
TCLR High to TAG Active
tRSQX
—
100
ns
STANDBY Setup to TCLR Low
tPDSR
30
—
ns
TCLR High to TWE Low
tRHWX
80
—
ns
TIMING LIMITS
Z0 = 50 Ω
OUTPUT
50 Ω
VL = 1.5 V
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
Thus, address setup time is shown as a minimum since
the system must supply at least that much time. On the
other hand, responses from the memory are specified
from the device point of view. Thus, the access time is
shown as a maximum since the device never provides
data later than that time.
Figure 1. AC Test Load
MPC2105C•MPC2106C
14
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
MPC2105C•MPC2106C
15
VALID
t AVMV
t AXMX
MATCH VALID
t KHML
t KHWX
t WVKH
t KHMV
t KHWX
t WVKH
VALID MATCH DATA FROM: PROCESSOR
* Cache addresses used are: A13 – A26 for MPC2105C, A12 – A26 for MPC2106C.
MATCH
TG
TWE
A0 – A11
A(12, 13 – 26*
CLK
VALID
t GLML
t WVKH
VALID ADDRESS
TAG RAM MATCH CYCLE
TAG RAM
VALID
t GLMX
PROCESSOR
TAG RAM TCLR FUNCTION
CLK
tHTC
tSTC
TCLR
tSHRS
tSRST
DIRTYOUT
tRHWX
tWVKH
TWE
tRSMV
MATCH
VALID
tRSQZ*
tRSQX
A0 – A11
* Transition is measured plus or minus 200 mV from steady state.
ORDERING INFORMATION
(Order by Full Part Number)
MPC
210xC
Motorola Memory Prefix
Part Number
Full Part Numbers — MPC2105CDG66
MPC2106CDG66
MPC2105C•MPC2106C
16
XX
XX
Speed (66 = 66 MHz)
Package (DG = Gold Pad DIMM)
MPC2105C = 512KB, synchronous
MPC2106C = 1MB, synchronous
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
178 LEAD CARD EDGE
MPC2105C
CASE 1132A–01
D
0.006
2X
D1
B C A
M
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
E
COMPONENT
AREA
A
2X
A1
1
24 25
47
48
R
VIEW A
D7
0.006 M C B A
D5
VIEW A
NOTE 4
E1
NOTE 5
E2
0.016
M
NOTES 3 AND 6
L
C
D4
D3
D2
A5
89
R
D6
A
B
2X
L
CL
SIDE VIEW
FRONT VIEW
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
90
178
COMPONENT
AREA
BACK VIEW
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉ
ÉÉ
ÉÉÉÉ
ÉÉ
É
ÉÉÉ
ÉÉ
ÉÉÉÉ
ÉÉ
É
CL
1
A2
A3
47
b
C B A
48
A4
178X
0.006
L
L
4X
86X
VIEW A
MOTOROLA FAST SRAM
e1
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN INCHES.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS E AND A5 DEFINE A
DOUBLE–SIDED MODULE.
5. DIMENSION E1 DEFINES OPTIONAL
SINGLE–SIDED MODULE.
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
DIM
A
A1
A2
A3
A4
A5
b
D
D1
D2
D3
D4
D5
D6
D7
e
e1
E
E1
E2
INCHES
MIN
MAX
1.190
1.210
0.545
–––
0.095
–––
–––
0.010
0.195
–––
0.195
–––
0.039
0.043
5.055
5.065
0.100
–––
0.190
–––
1.255
1.265
3.405
3.410
1.250 BSC
0.072
0.076
0.075
0.081
0.050 BSC
0.075 BSC
–––
0.210
–––
0.140
0.055
0.070
MPC2105C•MPC2106C
17
178 LEAD CARD EDGE
MPC2106C
CASE 1132–01
D
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
É
0.006
2X
D1
B C A
M
L
CL
E
COMPONENT
AREA
A
2X
A1
1
24 25
VIEW A
D7
0.006 M C B A
D5
NOTE 4
E1
NOTE 5
E2
0.016
M
NOTES 3 AND 6
L
C
D4
D3
D2
A5
89
R
VIEW A
2X
48
R
D6
A
B
47
SIDE VIEW
FRONT VIEW
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
ÉÉ
É
ÉÉ
É
ÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉ
90
178
COMPONENT
AREA
BACK VIEW
CL
ÉÉÉÉÉ
ÉÉÉÉÉ
É
ÉÉ
É
É
É
ÉÉ
É
ÉÉÉÉÉÉ
ÉÉ
É
1
A2
A3
47
b
C B A
48
A4
178X
0.006
L
L
4X
86X
VIEW A
e1
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN INCHES.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS E AND A5 DEFINE A
DOUBLE–SIDED MODULE.
5. DIMENSION E1 DEFINES OPTIONAL
SINGLE–SIDED MODULE.
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
DIM
A
A1
A2
A3
A4
A5
b
D
D1
D2
D3
D4
D5
D6
D7
e
e1
E
E1
E2
INCHES
MIN
MAX
1.390
1.410
0.545
–––
0.095
–––
–––
0.010
0.195
–––
0.195
–––
0.039
0.043
5.055
5.065
0.100
–––
0.190
–––
1.255
1.265
3.405
3.410
1.250 BSC
0.072
0.076
0.075
0.081
0.050 BSC
0.075 BSC
–––
0.210
–––
0.140
0.055
0.070
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MPC2105C•MPC2106C
18
◊
MPC2105C/D
MOTOROLA FAST
SRAM