MOTOROLA MMBT5089LT1

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by MMBT5088LT1/D
SEMICONDUCTOR TECHNICAL DATA
COLLECTOR
3
NPN Silicon
*Motorola Preferred Device
1
BASE
2
EMITTER
MAXIMUM RATINGS
3
1
Rating
Symbol
5088LT1
5089LT1
Unit
Collector – Emitter Voltage
VCEO
30
25
Vdc
Collector – Base Voltage
VCBO
35
30
Vdc
Emitter – Base Voltage
VEBO
4.5
Vdc
IC
50
mAdc
Symbol
Max
Unit
Total Device Dissipation FR– 5 Board(1)
TA = 25°C
Derate above 25°C
PD
225
mW
1.8
mW/°C
Thermal Resistance, Junction to Ambient
RqJA
556
°C/W
PD
300
mW
2.4
mW/°C
RqJA
417
°C/W
TJ, Tstg
– 55 to +150
°C
Collector Current — Continuous
2
CASE 318 – 08, STYLE 6
SOT– 23 (TO – 236AB)
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation
Alumina Substrate,(2) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
MMBT5088LT1 = 1Q; MMBT5089LT1 = 1R
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
30
25
—
—
35
30
—
—
—
—
50
50
—
—
50
100
Unit
OFF CHARACTERISTICS
Collector – Emitter Breakdown Voltage
(IC = 1.0 mAdc, IB = 0)
Collector – Base Breakdown Voltage
(IC = 100 mAdc, IE = 0)
V(BR)CEO
MMBT5088
MMBT5089
V(BR)CBO
MMBT5088
MMBT5089
Collector Cutoff Current
(VCB = 20 Vdc, IE = 0)
(VCB = 15 Vdc, IE = 0)
MMBT5088
MMBT5089
Emitter Cutoff Current
(VEB(off) = 3.0 Vdc, IC = 0)
(VEB(off) = 4.5 Vdc, IC = 0)
MMBT5088
MMBT5089
0.062 in.
0.024 in. 99.5% alumina.
Vdc
Vdc
ICBO
nAdc
IEBO
nAdc
1. FR– 5 = 1.0
0.75
2. Alumina = 0.4 0.3
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
 Motorola, Inc. 1996
1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic
Symbol
Min
Max
MMBT5088
MMBT5089
300
400
900
1200
(IC = 1.0 mAdc, VCE = 5.0 Vdc)
MMBT5088
MMBT5089
350
450
—
—
(IC = 10 mAdc, VCE = 5.0 Vdc)
MMBT5088
MMBT5089
300
400
—
—
—
0.5
—
0.8
50
—
—
4.0
—
10
350
450
1400
1800
—
—
3.0
2.0
Unit
ON CHARACTERISTICS
DC Current Gain
(IC = 100 µAdc, VCE = 5.0 Vdc)
hFE
Collector – Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
VCE(sat)
Base – Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
VBE(sat)
—
Vdc
Vdc
SMALL– SIGNAL CHARACTERISTICS
Current – Gain — Bandwidth Product
(IC = 500 µAdc, VCE = 5.0 Vdc, f = 20 MHz)
fT
Collector–Base Capacitance
(VCB = 5.0 Vdc, IE = 0, f = 1.0 MHz emitter guarded)
Ccb
Emitter–Base Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz collector guarded)
Ceb
Small Signal Current Gain
(IC = 1.0 mAdc, VCE = 5.0 Vdc, f = 1.0 kHz)
MHz
pF
pF
hfe
MMBT5088
MMBT5089
Noise Figure
(IC = 100 mAdc, VCE = 5.0 Vdc, RS = 10 kΩ, f = 1.0 kHz)
RS
—
NF
MMBT5088
MMBT5089
dB
in
en
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
NOISE CHARACTERISTICS
(VCE = 5.0 Vdc, TA = 25°C)
NOISE VOLTAGE
30
30
BANDWIDTH = 1.0 Hz
BANDWIDTH = 1.0 Hz
20
RS ≈ 0
IC = 10 mA
en , NOISE VOLTAGE (nV)
en , NOISE VOLTAGE (nV)
20
3.0 mA
10
1.0 mA
7.0
5.0
RS ≈ 0
f = 10 Hz
10
100 Hz
7.0
10 kHz
1.0 kHz
5.0
300 µA
3.0
10
20
50 100 200
3.0
0.01 0.02
500 1 k 2 k 5 k 10 k 20 k 50 k 100 k
f, FREQUENCY (Hz)
Figure 2. Effects of Frequency
IC = 10 mA
3.0 mA
1.0 mA
300 µA
100 µA
0.3
0.2
RS ≈ 0
0.1
10
20
10 µA
50 100 200
10
16
3.0
1.0
0.7
0.5
5.0
20
BANDWIDTH = 1.0 Hz
2.0
0.05 0.1 0.2
0.5 1.0
2.0
IC, COLLECTOR CURRENT (mA)
Figure 3. Effects of Collector Current
NF, NOISE FIGURE (dB)
In, NOISE CURRENT (pA)
10
7.0
5.0
100 kHz
BANDWIDTH = 10 Hz to 15.7 kHz
12
500 µA
8.0
IC = 1.0 mA
100 µA
10 µA
4.0
30 µA
0
10
500 1 k 2 k 5 k 10 k 20 k 50 k 100 k
f, FREQUENCY (Hz)
20
Figure 4. Noise Current
50 100 200 500 1 k 2 k
5 k 10 k 20 k 50 k 100 k
RS, SOURCE RESISTANCE (OHMS)
Figure 5. Wideband Noise Figure
100 Hz NOISE DATA
20
BANDWIDTH = 1.0 Hz
IC = 10 mA
16
100 µA
100
70
50
3.0 mA
1.0 mA
30
300 µA
20
10
7.0
5.0
30 µA
10 µA
NF, NOISE FIGURE (dB)
VT, TOTAL NOISE VOLTAGE (nV)
300
200
IC = 10 mA
3.0 mA
1.0 mA
12
300 µA
8.0
100 µA
30 µA
4.0
10 µA
BANDWIDTH = 1.0 Hz
0
3.0
10
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k 50 k 100 k
RS, SOURCE RESISTANCE (OHMS)
Figure 6. Total Noise Voltage
Motorola Small–Signal Transistors, FETs and Diodes Device Data
10
20
50 100 200 500 1 k 2 k 5 k 10 k 20 k 50 k 100 k
RS, SOURCE RESISTANCE (OHMS)
Figure 7. Noise Figure
3
h FE, DC CURRENT GAIN (NORMALIZED)
4.0
3.0
VCE = 5.0 V
2.0
TA = 125°C
25°C
1.0
– 55°C
0.7
0.5
0.4
0.3
0.2
0.01
0.02
0.03
0.05
0.1
0.2
0.3
0.5
IC, COLLECTOR CURRENT (mA)
1.0
2.0
3.0
5.0
10
Figure 8. DC Current Gain
1.0
RθVBE, BASE–EMITTER
TEMPERATURE COEFFICIENT (mV/ °C)
– 0.4
TJ = 25°C
V, VOLTAGE (VOLTS)
0.8
0.6
VBE @ VCE = 5.0 V
0.4
0.2
– 0.8
– 1.2
TJ = 25°C to 125°C
– 1.6
– 2.0
– 55°C to 25°C
VCE(sat) @ IC/IB = 10
0
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20
IC, COLLECTOR CURRENT (mA)
50
– 2.4
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10
IC, COLLECTOR CURRENT (mA)
100
8.0
C, CAPACITANCE (pF)
6.0
TJ = 25°C
Cob
4.0
3.0
Ceb
Cib
Ccb
2.0
1.0
0.8
0.1
0.2
1.0
2.0
5.0
0.5
10
20
VR, REVERSE VOLTAGE (VOLTS)
Figure 11. Capacitance
4
50 100
Figure 10. Temperature Coefficients
50
100
f T, CURRENT–GAIN — BANDWIDTH PRODUCT (MHz)
Figure 9. “On” Voltages
20
500
300
200
100
VCE = 5.0 V
TJ = 25°C
70
50
1.0
2.0
3.0
5.0 7.0 10
20 30
IC, COLLECTOR CURRENT (mA)
50 70 100
Figure 12. Current–Gain — Bandwidth Product
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by T J(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA . Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD =
150°C – 25°C
556°C/W
= 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
B S
1
V
2
DIM
A
B
C
D
G
H
J
K
L
S
V
G
C
H
D
K
J
CASE 318–08
SOT–23 (TO–236AB)
ISSUE AE
INCHES
MIN
MAX
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
MILLIMETERS
MIN
MAX
2.80
3.04
1.20
1.40
0.89
1.11
0.37
0.50
1.78
2.04
0.013
0.100
0.085
0.177
0.45
0.60
0.89
1.02
2.10
2.50
0.45
0.60
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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6
◊
Motorola Small–Signal Transistors, FETs and Diodes Device
Data
MMBT5088LT1/D