Order this document by MMBTA13LT1/D SEMICONDUCTOR TECHNICAL DATA NPN Silicon COLLECTOR 3 *Motorola Preferred Device BASE 1 3 EMITTER 2 1 MAXIMUM RATINGS 2 Rating Symbol Value Unit Collector – Emitter Voltage VCES 30 Vdc Collector – Base Voltage VCBO 30 Vdc Emitter – Base Voltage VEBO 10 Vdc IC 300 mAdc Symbol Max Unit Total Device Dissipation FR– 5 Board(1) TA = 25°C Derate above 25°C PD 225 mW 1.8 mW/°C Thermal Resistance Junction to Ambient RqJA 556 °C/W PD 300 mW 2.4 mW/°C RqJA 417 °C/W TJ, Tstg – 55 to +150 °C Collector Current — Continuous CASE 318 – 08, STYLE 6 SOT– 23 (TO – 236AB) THERMAL CHARACTERISTICS Characteristic Total Device Dissipation Alumina Substrate,(2) TA = 25°C Derate above 25°C Thermal Resistance Junction to Ambient Junction and Storage Temperature DEVICE MARKING MMBTA13LT1 = 1M; MMBTA14LT1 = 1N ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)CES 30 — Vdc Collector Cutoff Current (VCB = 30 Vdc, IE = 0) ICBO — 100 nAdc Emitter Cutoff Current (VEB = 10 Vdc, IC = 0) IEBO — 100 nAdc OFF CHARACTERISTICS Collector – Emitter Breakdown Voltage (IC = 100 mAdc, VBE = 0) 0.062 in. 0.024 in. 99.5% alumina. 1. FR– 5 = 1.0 0.75 2. Alumina = 0.4 0.3 Thermal Clad is a trademark of the Bergquist Company Preferred devices are Motorola recommended choices for future use and best overall value. Motorola Small–Signal Transistors, FETs and Diodes Device Data Motorola, Inc. 1996 1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Characteristic Symbol Min Max Unit MMBTA13 MMBTA14 5000 10,000 — — MMBTA13 MMBTA14 10,000 20,000 — — VCE(sat) — 1.5 Vdc VBE — 2.0 Vdc fT 125 — MHz ON CHARACTERISTICS(3) DC Current Gain (IC = 10 mAdc, VCE = 5.0 Vdc) hFE (IC = 100 mAdc, VCE = 5.0 Vdc) Collector – Emitter Saturation Voltage (IC = 100 mAdc, IB = 0.1 mAdc) Base – Emitter On Voltage (IC = 100 mAdc, VCE = 5.0 Vdc) — SMALL– SIGNAL CHARACTERISTICS Current – Gain — Bandwidth Product(4) (IC = 10 mAdc, VCE = 5.0 Vdc, f = 100 MHz) 3. Pulse Test: Pulse Width 4. fT = |hfe| • ftest. v 300 ms, Duty Cycle v 2.0%. RS in en IDEAL TRANSISTOR Figure 1. Transistor Noise Model 2 Motorola Small–Signal Transistors, FETs and Diodes Device Data NOISE CHARACTERISTICS (VCE = 5.0 Vdc, TA = 25°C) 500 2.0 BANDWIDTH = 1.0 Hz RS ≈ 0 i n, NOISE CURRENT (pA) en, NOISE VOLTAGE (nV) 200 BANDWIDTH = 1.0 Hz 100 10 µA 50 100 µA 20 IC = 1.0 mA 10 1.0 0.7 0.5 IC = 1.0 mA 0.3 0.2 100 µA 0.1 0.07 0.05 10 µA 0.03 0.02 10 20 5.0 10 20 50 100 200 500 1 k 2 k 5 k 10 k 20 k f, FREQUENCY (Hz) 50 k 100 k 50 100 200 50 k 100 k Figure 3. Noise Current 14 200 BANDWIDTH = 10 Hz TO 15.7 kHz 12 BANDWIDTH = 10 Hz TO 15.7 kHz 100 NF, NOISE FIGURE (dB) VT, TOTAL WIDEBAND NOISE VOLTAGE (nV) Figure 2. Noise Voltage 500 1 k 2 k 5 k 10 k 20 k f, FREQUENCY (Hz) IC = 10 µA 70 50 100 µA 30 20 1.0 mA 10 1.0 2.0 10 10 µA 8.0 100 µA 6.0 4.0 IC = 1.0 mA 2.0 5.0 10 20 50 100 200 RS, SOURCE RESISTANCE (kΩ) 500 100 0 Figure 4. Total Wideband Noise Voltage Motorola Small–Signal Transistors, FETs and Diodes Device Data 0 1.0 2.0 5.0 10 20 50 100 200 RS, SOURCE RESISTANCE (kΩ) 500 100 0 Figure 5. Wideband Noise Figure 3 SMALL–SIGNAL CHARACTERISTICS 4.0 |h fe |, SMALL–SIGNAL CURRENT GAIN 20 C, CAPACITANCE (pF) TJ = 25°C 10 7.0 Cibo Cobo 5.0 3.0 2.0 0.04 0.1 0.2 0.4 1.0 2.0 4.0 10 VR, REVERSE VOLTAGE (VOLTS) 20 2.0 1.0 0.8 0.6 0.4 0.2 0.5 40 200 k hFE, DC CURRENT GAIN TJ = 125°C 25°C 30 k 20 k 10 k 7.0 k 5.0 k – 55°C VCE = 5.0 V 3.0 k 2.0 k 5.0 7.0 10 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (mA) 500 RθV, TEMPERATURE COEFFICIENTS (mV/°C) TJ = 25°C V, VOLTAGE (VOLTS) 1.4 VBE(sat) @ IC/IB = 1000 1.2 VBE(on) @ VCE = 5.0 V 1.0 0.8 VCE(sat) @ IC/IB = 1000 0.6 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (mA) Figure 10. “On” Voltages 4 0.5 10 20 50 100 200 IC, COLLECTOR CURRENT (mA) 500 TJ = 25°C 2.5 IC = 10 mA 50 mA 250 mA 500 mA 2.0 1.5 1.0 0.5 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 IB, BASE CURRENT (µA) 500 1000 Figure 9. Collector Saturation Region 1.6 10 2.0 3.0 Figure 8. DC Current Gain 5.0 7.0 1.0 Figure 7. High Frequency Current Gain VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS) Figure 6. Capacitance 100 k 70 k 50 k VCE = 5.0 V f = 100 MHz TJ = 25°C 500 – 1.0 – 2.0 *APPLIES FOR IC/IB ≤ hFE/3.0 25°C TO 125°C *RqVC FOR VCE(sat) – 55°C TO 25°C – 3.0 25°C TO 125°C – 4.0 qVB FOR VBE – 5.0 – 55°C TO 25°C – 6.0 5.0 7.0 10 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (mA) Figure 11. Temperature Coefficients Motorola Small–Signal Transistors, FETs and Diodes Device Data 500 r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.7 0.5 D = 0.5 0.2 0.3 0.2 0.1 0.05 SINGLE PULSE 0.1 0.07 0.05 SINGLE PULSE ZθJC(t) = r(t) • RθJC TJ(pk) – TC = P(pk) ZθJC(t) ZθJA(t) = r(t) • RθJA TJ(pk) – TA = P(pk) ZθJA(t) 0.03 0.02 0.01 0.1 0.2 0.5 1.0 2.0 10 5.0 20 50 t, TIME (ms) 100 200 500 1.0 k 2.0 k 5.0 k 10 k Figure 12. Thermal Response IC, COLLECTOR CURRENT (mA) 1.0 k 700 500 300 200 FIGURE A 1.0 ms tP TA = 25°C TC = 25°C 100 µs PP 1.0 s 100 70 50 PP t1 30 CURRENT LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT 20 10 0.4 0.6 1/f DUTY CYCLE 1.0 2.0 4.0 6.0 10 20 VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) Figure 13. Active Region Safe Operating Area 40 + t1 f + ttP1 PEAK PULSE POWER = PP Design Note: Use of Transient Thermal Resistance Data Motorola Small–Signal Transistors, FETs and Diodes Device Data 5 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T J(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. 6 SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. Motorola Small–Signal Transistors, FETs and Diodes Device Data PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 B S 1 V 2 G C D H K J CASE 318–08 ISSUE AE SOT–23 (TO–236AB) Motorola Small–Signal Transistors, FETs and Diodes Device Data DIM A B C D G H J K L S V INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR 7 Motorola reserves the right to make changes without further notice to any products herein. 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