MOTOROLA Order this document by MPC2104/D SEMICONDUCTOR TECHNICAL DATA Advance Information 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms MPC2104 MPC2105 MPC2106 MPC2107 The MPC2104/5/6/7 are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchronous data RAMs. The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18; the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the 5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst capability is provided in that two burst addresses bypass the address latch. Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in–depth description of the cache module. This EEPROM will be available on future revisions of the module family. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. • • • • • • • • • • • • • PowerPC–style Burst Counter on Chip (MPC2104/5/6) Flow–Through Data I/O (MPC2104/5/6) Plug and Pin Compatibility of entire Module Family Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6) Three State Outputs Byte Write Capability Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM (MPC2104/5/6) 15 ns for Data RAM (MPC2107) Decoupling Capacitors for Each Fast Static RAM High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes 182 Pin Card Edge Module Burndy Connector, Part Number: ELF182JSC–3Z50 BurstRAM is a trademark of Motorola. PowerPC is a trademark of International Business Machines Corp. This document contains information on a new product. Specifications and information herein are subject to change without notice. 11/8/95 Motorola, Inc. 1995 MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 1 PIN ASSIGNMENT 182–LEAD DIMM TOP VIEW – CASE TBD NOTES: 1. VCC5 and VCC3 must be connected on all modules. MPC2104•MPC2105•MPC2106•MPC2107 2 VSS PD1/IDSDATA PD3 DH31 DH29 DH27 DH25 VCC3 CWE3 DH23 DH21 DH18 VSS DH16 CWE2 DH14 DH13 VCC5 DH10 DH8 CWE1 DH6 VCC3 DH4 VSS CLK0 VSS DH1 CWE0 DL31 DL30 VSS DL29 DL27 DL25 VCC5 CWE7 DL23 DL21 DL19 VSS DL17 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 VSS PD0/IDSCLK PD2 DH30 DH28 DH26 DH24 VCC3 DP3 DH22 DH20 DH19 VSS DH17 DP2 DH15 DH12 VCC5 DH11 DH9 DP1 DH7 VCC3 DH5 DH3 DH2 DH0 DP0 VSS CLK1 VSS DL28 DL26 DL24 DP7 VCC5 DL22 DL20 DL18 DL16 VSS DP6 CWE6 DL15 DL13 VSS DL10 DL8 CWE5 DL6 VCC3 DL5 DL2 VSS CLK3 VSS CLK4 VSS CWE4 ALE VCC3 ADDR1 RESERVED CNTEN0 CNTEN1 VCC5 VCC5 A27 A24 A22 A20 VSS A18 A16 A15 A14 VCC3 A10 A8 A6 VSS A4 A2 A1 BURSTMODE VCC5 VALIDIN TWE STANDBY DIRTYOUT VSS 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 DL14 DL12 DL11 VSS DL9 DP5 DL7 DL4 VCC3 DL3 DL1 DL0 VSS CLK2 VSS DP4 COE0 COE1 VCC3 ADDR0 RESERVED ADS0 ADS1 VCC5 VCC5 A28 A26 A25 A23 VSS A21 A19 A17 A13 VCC3 A12 A11 A9 VSS A7 A5 A3 A0 VCC5 TCLR MATCH TOE DIRTYIN VSS MOTOROLA FAST SRAM MPC2104/MPC2105 BLOCK DIAGRAM A28 A27 A14 – A26 A13 A0 MCM67Mx18 A2 – A14 A15 ’244 ADS0 CNTEN0 COE0 CLK3 CLK4 ALE ADS1 CNTEN1 COE1 ADDR0 ADDR1 PD2 PD3 CLK0 K A1 DQ0 – DQ8 DH0 – DH7 + DP0 DQ9 – DQ17 TSC LW DH8 – DH15 + DP1 CWE0 BAA UW CWE1 G STANDBY E TSP VCC5 via 100 Ω A0 = NC = NC = NC = NC = NC = NC = NC = NC = NC J4 MCM67Mx18 CLK0 K A1 A2 – A14 A15 DQ0 – DQ8 DH16 – DH23 + DP2 DQ9 – DQ17 TSC LW DH24 – DH31 + DP3 CWE2 BAA UW CWE3 G PD0/IDSCLK E TSP PD1/IDSDATA X24C00 (OPTIONAL) SCL SDA J2 J3 A0 MCM67Mx18 A1 A2 – A14 A15 CLK1 K DL0 – DL7 + DP4 DL8 – DL15 + DP5 DQ0 – DQ8 DQ9 – DQ17 TSC BAA LW UW CWE4 K CLK1 CWE5 G E TSP A0 MCM67Mx18 A1 A2 – A14 A15 DL16 – DL23 + DP6 DL24 – DL31 + DP7 DQ0 – DQ8 DQ9 – DQ17 CWE6 LW UW TSC BAA CWE7 G E TSP TAG: 16K x 12 + V + D J1 J0 A14 – A26 A2 – A12 A1 J5 TCLR TWE CLK2 VALIDIN DIRTYIN TOE J5 J4 J3 J2 J1 J0 A13 A0 – A12 TDQ0 – TDQ10 TDQ11 RESET SW TW K VALIDD DIRTYD TG TT1, WTD, E1 SFUNC, SG TAG, TAD, E2 TAH, PWRDN MATCH DIRTYQ 256KB 512KB no stuff 0Ω 0Ω 0Ω 0Ω no stuff 0Ω 0Ω 0Ω no stuff no stuff 0Ω EEPROM 256KB no stuff no stuff no stuff no stuff 0Ω no stuff EEPROM 512KB 0Ω no stuff no stuff no stuff no stuff 0Ω VSS VCC5 via 100 Ω MATCH DIRTYOUT VCCQ VALIDQ WTQ VCC3 NC NC Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs. MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 3 MPC2106 BLOCK DIAGRAM A13 – A28 ADS0 CNTEN0 COE0 ’244 PA12 A12 STANDBY 64K X 18 BURST A0 – A15 K TSC DQ0 – DQ8 BAA DQ9 – DQ17 G LW UW E CLK0 DH0 – DH7 + DP0 DH8 – DH15 + DP1 CWE0 CWE1 PAL PD0/IDSCLK K A0 – A15 TSC DQ0 – DQ8 DQ9 – DQ17 BAA LW G E UW 64K X 18 BURST A0 – A15 K TSC DQ0 – DQ8 BAA DQ9 – DQ17 G LW E UW 64K X 18 BURST A0 – A15 TSC BAA G E K DQ0 – DQ8 DQ9 – DQ17 LW UW 64K X 18 BURST ADS1 CNTEN1 COE1 K A0 – A15 DQ0 – DQ8 TSC DQ9 – DQ17 BAA LW G UW E 64K X 18 BURST A0 – A15 K TSC DQ0 – DQ8 BAA DQ9 – DQ17 G LW E UW CLK1 DH16 – DH23 + DP2 DH24 – DH31 + DP3 CWE2 CWE3 TAG: 16K x 12 + V + D A13 – A26 14 A0 – A11 TCLR CLK3 DL0 – DL7 + DP4 TWE DL8 – DL15 + DP5 CLK2 CWE4 VALIDIN CWE5 DIRTYIN TOE TT1, WTD A0 – A13 TDQ0 – TDQ11 SFUNC, SG TAH, TAG, TAD RESET PWRDN SW MATCH TW DIRTYQ K VALIDD VCCQ DIRTYD TA, VALIDQ TG WTQ E1 E2 CLK4 DL16 – DL23 + DP6 DL24 – DL31 + DP7 CWE6 CWE7 VSS VCC5 via 100 Ω MATCH DIRTYOUT VCC3 NC NC A12 VDD TAG: 16K x 12 + V + D A13 – A26 A0 – A11 A0 – A13 TT1, WTD TDQ0 – TDQ11 SFUNC, SG RESET TAH, TAG, TAD PWRDN SW MATCH TW DIRTYQ K VALIDD VCCQ DIRTYD TA, VALIDQ TG WTQ TCLR CLK0 DH0 – DH7 + DP0 TWE DH8 – DH15 + DP1 CLK2 CWE0 VALIDIN CWE1 DIRTYIN TOE E1 E2 CLK1 DH16 – DH23 + DP2 DH24 – DH31 + DP3 CWE2 CWE3 ALE ADDR0 ADDR1 PD2 PD3 64K X 18 BURST A0 – A15 K TSC DQ0 – DQ8 BAA DQ9 – DQ17 G LW E UW X24C00 (OPTIONAL) SCL SDA J0 64K X 18 BURST PA12L PD1/IDSDATA CLK3 DL0 – DL7 + DP4 DL8 – DL15 + DP5 CWE4 CWE5 VSS VCC5 via 100 Ω MATCH DIRTYOUT VCC3 NC NC VSS A12 = NC = NC = NC = NC J1 64K X 18 BURST A0 – A15 TSC BAA G E K DQ0 – DQ8 DQ9 – DQ17 LW UW CLK4 DL16 – DL23 + DP6 DL24 – DL31 + DP7 CWE6 CWE7 J1 J0 1M 0Ω 0Ω EEPROM 1M no stuff no stuff Note: All 64K X 18 TSP signals are tied to VCC via a 100 Ω resistor. Edge connector A28 connects to the 64K x 18 A0; edge connector A27 connects to the 64K x 18 A1. MPC2104•MPC2105•MPC2106•MPC2107 4 MOTOROLA FAST SRAM MPC2107 BLOCK DIAGRAM ADDR0 ADDR1 A14 – A26 A0 A1 ’373 ALE COE0 STANDBY MCM6206 A2 – A14 DQ0 – DQ7 W G E A0 A1 PD0/IDSCLK DQ0 – DQ7 W DQ0 – DQ7 W G E DQ0 – DQ7 W G E DQ0 – DQ7 W G E DQ0 – DQ7 W G E DQ0 – DQ7 W G E MOTOROLA FAST SRAM TCLR TWE CLK2 VALIDIN DIRTYIN TOE DQ0 – DQ7 W TAG: 16K x 12 + V + D A13 A0 – A12 TT1, WTD, E1 TDQ0 – TDQ11 SFUNC, SG RESET TAH, TAG, TAD E2, PWRDN SW MATCH TW DIRTYQ K VALIDD VCCQ DIRTYD TA, VALIDQ TG WTQ VSS VCC5 via 100 Ω MATCH DIRTYOUT VCC3 NC NC DL0 – DL7 CWE4 CLK0, 1, 3, 4 ADS0, ADS1 CNTEN0, CNTEN1 A27, A28 DP0 – DP7 BURSTMODE PD2 PD3 DL8 – DL15 CWE5 = NC = NC = NC = NC = NC = NC = NC J1 DL16 – DL23 CWE6 J3 J2 J1 MCM6206 A2 – A14 G E DH24 – DH31 CWE3 MCM6206 A2 – A14 A0 A1 VSS A14 – A26 13 A2 – A13 MCM6206 A2 – A14 A0 A1 DH16 – DH23 CWE2 MCM6206 A2 – A14 A0 A1 DH8 – DH15 CWE1 MCM6206 A2 – A14 COE1 SCL SDA MCM6206 A2 – A14 A0 A1 X24C00 (OPTIONAL) J3 G E A0 A1 PD1/IDSDATA J2 MCM6206 A2 – A14 A0 A1 DH0 – DH7 CWE0 256KB 0Ω 0Ω 0Ω EEPROM 256KB no stuff no stuff no stuff DL24 – DL31 CWE7 MPC2104•MPC2105•MPC2106•MPC2107 5 PIN DESCRIPTIONS Pin Locations Symbol Type 68, 69, 70, 71, 73, 74, 75, 76, 78, 79, 80, 82, 83, 84, 85, 159, 160, 161, 162, 164, 165, 166, 167, 169, 170, 171, 173, 174, 175 A0 – A28 Input Address Inputs – (MSB:0, LSB:28) 62 ADDR0 Input Least significant address bit when asynchronous Data RAMs are used. Description 153 ADDR1 Input Next to least significant address bit when asynchronous Data RAMs are used. 30, 56, 117, 146, 148 CLK0 – CLK4 Input Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only. For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0–CLK2 only. For MPC2107 use CLK2 only. 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 27, 95, 96, 97, 98, 101, 102, 103, 105, 107, 108, 110, 111, 113, 115, 119 DH0 – DH31 I/O High Data Bus – (MSB:0, LSB:31) 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 121, 122, 124, 125, 126, 129, 130, 131, 133, 135, 136, 138, 139, 141, 143, 144 DL0 – DL31 I/O Low Data Bus – (MSB:0, LSB:31) 9, 15, 21, 28, 35, 42, 48, 58 DP0 – DP7 I/O Data Parity Bits – (MSB:0, LSB:7) 3, 94 PD2, PD3 Output 2 PD0/IDSCLK Input Presence detect bit 0/EEPROM serial clock. (EEPROM option only.) 93 PD1/IDSDATA I/O Presence detect bit 1/EEPROM serial data. (EEPROM option only.) 64, 65 ADS0, ADS1 Input Data RAM Address Strobe – For MPC2104 or MPC2105 use ADS0 only. For MPC2106 use ADS0, ADS1. 151 ALE Input Data RAM Address Latch Enable – Use for asynchronous Data RAM only. 155, 156 CNTEN0, CNTEN1 Input Data RAM Count Enables – For MPC2104 or MPC2105 use CNTEN0 only. For MPC2106 use CNTEN0, CNTEN1. 59, 60 COE0, COE1 Input Data RAM Output Enables – For MPC2104 or MPC2105 use COE0 only. For all others use COE0, COE1. 100, 106, 112, 120, 128, 134, 140, 150 CWE0 – CWE7 Input Data RAM Write Enables – (MSB:0, LSB:7) 87 TCLR Input Tag RAM clear. 88 MATCH Output 178 VALIDIN Input Tag RAM valid bit. 179 TWE Input Tag RAM write enable. 89 TOE Input Tag RAM output enable. Dirty input bit. Presence detect bits. Tag RAM active high match indication. 90 DIRTYIN Input 181 DIRTYOUT Output 180 STANDBY Input 176, 63, 154 RESERVED 8, 23, 51, 61, 77, 99, 114, 142, 152, 168 VCC3 Input + 3.3 V power supply. Must be connected. 18, 36, 66, 67, 86, 109, 127, 157, 158, 177 VCC5 Input + 5 V power supply. Must be connected. 1, 13, 29, 31, 41, 46, 55, 57, 72, 81, 91, 92, 104, 116, 118, 123, 132, 137, 145, 147, 149, 163, 172, 182 VSS Input Ground 176 BURSTMODE Input Burstmode. 0 = Linear, 1 = Interleaved. MPC2104•MPC2105•MPC2106•MPC2107 6 Dirty output bit. Standby pin. Reduces standby power consumption. Reserved pin. MOTOROLA FAST SRAM DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) STANDBY ADS0 CNTEN0 CWEx CLKx Address Used Operation H L X X L–H N/A Deselected L L X L L–H External Address Write Cycle, Begin Burst L L X H L–H External Address Read Cycle, Begin Burst X H L L L–H Next Address Write Cycle, Continue Burst X H L H L–H Next Address Read Cycle, Continue Burst X H H L L–H Current Address Write Cycle, Suspend Burst X H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except COE must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation COE I/O Status Read L Data Out (DQ0 – DQ8) Read H High–Z Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, COE must be high before the input data required set–up time and held high through the input data hold time. DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) STANDBY COE0, COE1 CWE0 – CWE7 Operation I/O Status H X X Deselected High–Z L H H Output Disabled High–Z L L H Read Data Out L X L Write High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, COE0, and COE1 must be high before the input data required set–up time, and held high through the input data hold time. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Iout ± 30 ± 20 mA PD 8.1 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Data RAM Tag Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MOTOROLA FAST SRAM This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MPC2104•MPC2105•MPC2106•MPC2107 7 DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Symbol Min Supply Voltage (Operating Voltage Range) VCC Input High Voltage VIH Input Low Voltage VIL Parameter Max Unit 4.75 5.25 V 2.2 VCC + 0.3** V – 0.5* 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Parameter Data RAM Tag Ilkg(I) — ± 1.0 ± 5.0 µA Output Leakage Current (COE = VIH, Vout = 0 to VCC) Data RAM Tag Ilkg(O) — ± 1.0 ± 5.0 µA TTL Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V TTL Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol Max Unit POWER SUPPLY CURRENTS Parameter AC Supply Current (COE = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) ICCA MPC2104 MPC2105 MPC2106 MPC2107 mA 1480 1420 2840 1400 ISB1 MPC2104 MPC2105 MPC2106 MPC2107 mA 620 700 1400 960 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Symbol Typ Max Unit Cin — 16 8 — 15 20 10 5 pF (MATCH, DIRTYOUT) Cout — 7 pF (DH0 – DH31, DL0 – DL31) CI/O 6 8 pF (A0 – A11) CI/O — 7 pF Parameter Input Capacitance Tag Output Capacitance Data RAM Input/Output Capacitance Tag Input/Output Capacitance MPC2104•MPC2105•MPC2106•MPC2107 8 (A13 – A28) (Data RAM Control Pins) (CLK0 – CLK4) (Tag Control Pins) MOTOROLA FAST SRAM DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 7) MPC2104 MPC2105 MPC2106 Parameter Symbol Min Max Unit Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 9 ns Output Enable to Output Valid tGLQV — 5 ns Clock High to Output Active tKHQX1 6 — ns Clock High to Output Change tKHQX2 3 — ns Output Enable to Output Active tGLQX 0 — ns Output Disable to Q High–Z tGHQZ 2 6 ns Clock High to Q High–Z tKHQZ — 6 ns Clock High Pulse Width tKHKL 5 — ns Clock Low Pulse Width tKLKH 5 — ns tAVKH 7.5 — ns 5, 6 Setup Time Address Notes 4 Setup Times: Address Status Data In Write Address Advance Chip Enable tSVKH tDVKH tWVKH tBAVVKH tEVKH 2.5 — ns 5 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX 0.5 — ns 5 NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. All read and write cycle timings are referenced from CLK or COE. 3. COE is a don’t care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible PowerPC external bus cycles. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled. 6. 5 ns of set–up delay is incurred in address buffers. 7. Applies to MPC2104, MPC2105, and MPC2106. MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 9 SYNCHRONOUS DATA RAM READ CYCLE tKHKH CLK1, CLK0 tKLKH tKHKL ADS0 tTSVKH tAVKH A(12, 13, 14 – 26) (See Note 1) tKHTSX tKHAX A1 A2 CWE0 – CWE7 tKHWX tWVKH tEVKH tKHEX STANDBY tBAVKH tKHBAX CNTEN0 tKHQV tGLQV COE tGLQX tKHQX1 DATA OUT Q (A1) READ tGHQZ tKHQX2 Q (A2) tKHQZ tKHQV Q (A2 + 1) Q (A2 + 2) Q (A2 + 3) BURST READ NOTES: 1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106. 2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with A2 as the base address. MPC2104•MPC2105•MPC2106•MPC2107 10 MOTOROLA FAST SRAM SYNCHRONOUS DATA RAM WRITE CYCLE tKHKH CLK1, CLK0 tKLKH tKHKL tSVKH tKHTSX tAVKH tKHAX ADS0 tAVKH A(12, 13, 14 – 26) tKHAX A1 A2 tKHWX tWVKH CWE0 – CWE7 tEVKH tKHEX STANDBY tBAVKH tKHBAX CNTEN0 tDVKH DATA IN D (A1) SINGLE WRITE tKHDX D (A2) D (A2 + 1) D (A2 + 2) D (A2 + 3) BURST WRITE NOTES: 1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106. 2. COE0 = VIH MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 11 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted ASYNCHRONOUS DATA RAMs READ CYCLE TIMING (See Notes 1 and 8) MPC2107–15 Parameter Symbol Min Max Unit Notes Cycle Time tAVAV 15 — ns 2 Address Access Time tAVQV — 15 ns Enable Access Time tELQV — 15 ns Output Enable Access Time tGLQV — 8 ns Output Hold from Address Change tAXQX 4 — ns 4, 5, 6 Enable Low to Output Active tELQX 4 — ns 4, 5, 6 Enable High to Output High–Z tEHQZ 0 8 ns 4, 5, 6 Output Enable Low to Output Active tGLQX 0 — ns 4, 5, 6 Output Enable High to Output High–Z tGHQZ 0 7 ns 4, 5, 6 tELICCH 0 — ns Power Up Time 3 Power Down Time tEHICCL — 15 ns NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ(max) is less than tELQX(min), and tGHQZ(max) is less than tGLQX(min), both for a given device and from device to device. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, COE0 = VIL). 8. Applies to MPC2107. MPC2104•MPC2105•MPC2106•MPC2107 12 MOTOROLA FAST SRAM ASYNCHRONOUS READ CYCLE 1 (See Note 7) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV ASYNCHRONOUS READ CYCLE 2 (See Note 3) tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX Q (DATA OUT) HIGH–Z tELICCH HIGH–Z DATA VALID tEHICCL VCC SUPPLY CURRENT MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 13 ASYNCHRONOUS DATA RAMs WRITE CYCLE 1 (See Notes 1 and 2) MPC2107–15 Parameter Write Cycle Time Symbol Min Max Unit Notes tAVAV 15 — ns 3 Address Set–up Time tAVWL 0 — ns Address Valid to End of Write tAVWH 12 — ns Write Pulse Width tWLWH tWLEH 12 — ns Write Pulse Width, G High tWLWH tWLEH 10 — ns Data Valid to End of Write tDVWH 7 — ns Data Hold Time tWHDX 0 — ns Write Low to Output High–Z tWLQZ 0 7 ns 5,6,7 Write High to Output Active tWHQX 5 — ns 5,6,7 Write Recovery Time tWHAX 0 — ns 4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E ≥ VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tDVWH tAVWL D (DATA IN) tWHDX DATA VALID tWLQZ Q (DATA OUT) HIGH–Z HIGH–Z tWHQX MPC2104•MPC2105•MPC2106•MPC2107 14 MOTOROLA FAST SRAM ASYNCHRONOUS DATA RAMs WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MPC2107–15 Parameter Write Cycle Time Symbol Min Max Unit Notes tAVAV 15 — ns 0 Address Setup Time tAVEL 0 — ns Address Valid to End of Write tAVEH 12 — ns Enable to End of Write tELEH tELWH 10 — ns Data Valid to End of Write tDVEH 7 — ns Data Hold Time tEHDX 0 — ns Write Recovery Time tEHAX 0 — ns 3, 4 NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. ASYNCHRONOUS WRITE CYCLE 2 (E Controlled, See Note 1) tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tELEH tELWH tAVEL tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) Q (DATA OUT) MOTOROLA FAST SRAM tEHDX DATA VALID HIGH–Z MPC2104•MPC2105•MPC2106•MPC2107 15 TAG RAM RESET FUNCTION TRUTH TABLE (See Notes 1 and 2) L L–H H High–Z VLDout L(3) L L–H L — — TCLR CLK TWE TAG DTYout L(3) WTout L(3) MATCH TA Operation POWER L(3) High–Z Reset Status Active — — — — Not Allowed — NOTES: 1. H = VIH, L = VIL, X = don‘t care, — = unrelated. 2. TOE is X for this table. READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3) TOE TWE CLK TAG VLDin DTYin WTin VLDout DTYout WTout MATCH Operation L H X DOUT — — — — — — DOUT Read Tag I/O H X X High–Z — — — — — — — Tag I/O Disable WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2) TOE TWE CLK TAG VLDin DTYin WTin VLDout DTYout WTout MATCH Operation H L L–H DIN — — — DOUT DOUT DOUT L Write Tag I/O L L L–H — — — — — — — — Not Allowed NOTES: 1. H = VIH, L = VIL, X = don‘t care, — = unrelated. 2. This table applies when RESET and PWRDN are high. 3. DOUT in this case is the same as DIN. The input data is written through to the outputs during the write operation. MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4) TOE TWE TAG VLD(4) DTY(4) WT(4) MATCH Operation X X — — — — DOUT Selected L H DOUT — — — L Read Tag I/O H L DIN DIN DIN DIN L Write Tag I/O, Status Bits H H TAGIN L — — L Invalid Data – Dedicated Status Bits H H TAGIN H — — M Match – Dedicated Status Bits NOTES: 1. H = VIH, L = VIL, X = don‘t care, — = unrelated. 2. M = high if TAGIN equals the memory contents at the address; M = low if TAGIN does not equal the ocntents at that address. 3. PWRDN and RESET are high for this table. OES and CLK are X. 4. This column represents the stored memory cell data for the given status bit at the selected address. MPC2104•MPC2105•MPC2106•MPC2107 16 MOTOROLA FAST SRAM TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted TAG RAM READ CYCLE (See Notes 1 through 4) Tag RAM Parameter Symbol Min Max Unit Clock Access Time tKHQV — 10 ns Output Enable to Output Valid tGLQV — 8 ns Output Enable to Output Active tGLQX 0 — ns Output Disable to Q High–Z tGHQZ 1 6 ns Status Bit Hold from Address Change tAXSX 3 — ns Address Access Time Status Bits tAVSV — 10 ns Tag Bit Hold from Address Change tAVQX 3 — ns Address Access Time Tag Bits tAVQV — 12 ns Notes NOTES: 1. Set–up and hold times, W (write) referes to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag reads are asynchronous. TAG RAM WRITE CYCLE (See Notes 1 through 4) Tag RAM Parameter Symbol Min Max Unit Cycle Time tKHKH 15 — ns Clock High Pulse Width tKHKL 4.5 — ns Clock Low Pulse Width tKLKH 4.5 — ns Clock High to Output Active tKHQX 1.5 — ns Set–up Times Address Write tAVKH tWVKH 3 — ns Hold Times Address Write tKHAX tKHWX 1.5 — ns Status Output Hold tKHSX 0 — ns Clock High to Status Bits Valid tKHSV — 9 ns Notes NOTES: 1. Set–up and hold times, W (write) referes to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag writes are synchronous. MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 17 MPC2104•MPC2105•MPC2106•MPC2107 18 MOTOROLA FAST SRAM DIRTYOUT VALIDIN DIRTYIN A0 – A11 TOE TWE A(12, 13, 14–26) (See Note 3) CLK t WVKH t AVKH t WVKH t AVKH VALID t KHWX t KHAX t KHWX t WVKH t KHAX t KHKH t KHSV VALID INPUT VALID t KHSX t KLKH VALID t AXSX t AVSV t KHQX (See Note 1) t KHQV t KHWX TAG READ AFTER WRITE (See Note 1) t GHQZ VALID VALID OUTPUT VALID NOTE: 1. Transition is measured plus or minus 200 mV from steady state. 2. TCLR = High. 3. Cache addresses used are: 14–26 for MPC2004 and MPC2007; 13–26 for MPC2005; 12–26 for MPC2006 and MPC2009. t KHKL STATUS WRITE TAG WRITE TAG RAM WRITE AND READ CYCLES (See Note 2) t GLQX t GLQV VALID VALID OUTPUT VALID t AVSV t AXSX t AXQX t AVQV TAG READ AFTER READ VALID VALID OUTPUT TAG RAM MATCH CYCLE Tag RAM Parameter Symbol Min Max Unit Clock High Write to MATCH Invalid tKHML — 7 ns Clock High Read to MATCH Valid tKHMV — 10 ns Address Valid to MATCH Valid tAVMV — 10 ns MATCH Valid Hold from Address Change tAXMX 2 — ns TOE Low to MATCH Invalid tGLML — 7 ns TOE High to MATCH Valid tGHMX — 8 ns Symbol Min Max Unit TCLR Set–up Time tSTC 4 — ns TCLR Hold Time tHTC 1 — ns Status Bit Reset Time tSRST — 60 ns Status Bit Hold from TCLR Low tSHRS 2 — ns TCLR Low to MATCH Invalid tRSML — 10 ns TCLR High to MATCH Valid tRSMV — 100 ns TCLR Low to TAG High–Z tRSQZ — 10 ns TCLR High to TAG Active tRSQX — 100 ns STANDBY Set–up to TCLR Low tPDSR 30 — ns TCLR High to TWE Low tRHWX 80 — ns Notes TAG RAM RESET (TCLR) CYCLE Tag RAM Parameter TIMING LIMITS AC TEST LOADS +5 V 480 Ω Z0 = 50 Ω OUTPUT OUTPUT 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MOTOROLA FAST SRAM Notes Figure 1B The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. MPC2104•MPC2105•MPC2106•MPC2107 19 MPC2104•MPC2105•MPC2106•MPC2107 20 MOTOROLA FAST SRAM VALID t AVMV t AXMX MATCH VALID t KHML t KHWX t WVKH t KHMV t KHWX t WVKH VALID MATCH DATA FROM: PROCESSOR VALID t GLML t WVKH VALID ADDRESS * Cache addresses used are: 14–26 for MPC2004 and MPC2007; 13–26 for MPC2005; 12–26 for MPC2006. MATCH TOE TWE A0 – A11 A(12, 13, (14–26)* CLK TAG RAM MATCH CYCLE TAG RAM VALID t GLMX PROCESSOR TAG RAM TCLR FUNCTION CLK tHTC tSTC TCLR tSHRS tSRST DIRTYOUT tWVKH tRHWX TWE tRSMV MATCH VALID tRSQZ* tRSQX A0 – A11 * Transition is measured plus or minus 200 mV from steady state. MOTOROLA FAST SRAM MPC2104•MPC2105•MPC2106•MPC2107 21 ORDERING INFORMATION (Order by Full Part Number) MPC 210x Motorola Memory Prefix Part Number Full Part Numbers — MPC2104SG66 MPC2105SG66 MPC2106SG66 MPC2107SG15 XX XX Speed (66 = 66 MHz, synchronous) (15 = 15 ns asynchronous) Package (SG = Gold Pad SIMM) MPC2104 = 256KB, synchronous MPC2105 = 512KB, synchronous MPC2106 = 1MB, synchronous MPC2107 = 256KB, asynchronous Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] – TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MPC2104•MPC2105•MPC2106•MPC2107 ◊ 24 *MPC2104/D* MOTOROLA FAST SRAM MPC2104/D