MOTOROLA MCM6706RJ7

MOTOROLA
Order this document
by MCM6706R/D
SEMICONDUCTOR TECHNICAL DATA
32K x 8 Bit Static Random Access
Memory
The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
•
•
•
•
•
Single 5.0 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706R–6 = 6 ns
MCM6706R–7 = 7 ns
MCM6706R–8 = 8 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A
VCC
VSS
A
A
A
A
MEMORY
MATRIX
512 ROWS x 64 x 8
COLUMNS
ROW
DECODER
A
MCM6706R
J PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
A0
1
32
NC
A1
2
31
A14
A2
3
30
A13
A3
4
29
A12
E
5
28
G
DQ0
6
27
DQ7
DQ1
7
26
DQ6
VCC
8
25
VSS
VSS
9
24
VCC
DQ2
10
23
DQ5
DQ3
11
22
DQ4
W
12
21
A11
A4
13
20
A10
A5
14
19
A9
A6
15
18
A8
A7
16
17
NC
A
A
A
PIN NAMES
DQ0
COLUMN I/O
COLUMN DECODER
INPUT
DATA
CONTROL
DQ7
A
A
A
A
A
A
A0 – A14 . . . . . . . . . . . . . . . . . . Address
W . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ7 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
E
W
G
REV 1
5/95
 Motorola, Inc. 1995
MOTOROLA
FAST SRAM
MCM6706R
1
TRUTH TABLE
E
G
W
Mode
I/O Pin
Cycle
H
L
L
L
X
H
L
X
X
H
H
L
Not Selected
Read
Read
Write
High–Z
High–Z
Dout
Din
—
—
Read Cycle
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current
Iout
± 30
mA
Power Dissipation
PD
2.0
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
Storage Temperature — Plastic
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
—
VCC + 0.3*
V
Input Low Voltage
VIL
– 0.5**
—
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)
Ilkg(O)
—
± 1.0
µA
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
DC CHARACTERISTICS
Parameter
POWER SUPPLY CURRENTS
Parameter
Symbol
6706R–6
6706R–7
6706R–8
Unit
Notes
AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax)
ICCA
205
200
195
mA
1, 2, 3
AC Standby Current (E = VIH, VCC = max, f = fmax)
ISB1
95
90
85
mA
1, 2. 3
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,
Vin ≤ VSS, or ≥ VCC – 0.2 V)
ISB2
20
20
20
mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
MCM6706R
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Max
Unit
Address Input Capacitance
Cin
5
pF
Control Pin Input Capacitance (E, G, W)
Cin
6
pF
Cout
6
pF
I/O Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE (See Notes 1 and 2)
MCM6706R–6
MCM6706R–7
MCM6706R–8
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
6
—
7
—
8
—
ns
3
Address Access Time
tAVQV
—
6
—
7
—
8
ns
Chip Enable Access Time
tELQV
—
6
—
7
—
8
ns
Output Enable Access Time
tGLQV
—
4
—
4
—
4
ns
Output Hold from Address Change
tAXQX
3
—
3
—
3
—
ns
Chip Enable Low to Output Active
tELQX
3
—
3
—
3
—
ns
4 ,5, 6
Chip Enable High to Output High–Z
tEHQZ
0
3
0
3.5
0
4
ns
4, 5, 6
Output Enable Low to Output Active
tGLQX
0
—
0
—
0
—
ns
4, 5, 6
Parameter
Output Enable High to Output High–Z
tGHQZ
0
3
0
3.5
0
4
ns
4, 5, 6
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIL).
8. Addresses valid prior to or coincident with E going low.
AC TEST LOADS
TIMING LIMITS
+5 V
480 Ω
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
OUTPUT
255 Ω
5 pF
VL = 1.5 V
Figure 1A
MOTOROLA FAST SRAM
Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
MCM6706R
3
READ CYCLE 1 (See Note 7)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
DATA VALID
PREVIOUS DATA VALID
tAVQV
READ CYCLE 2 (See Note 8)
tAVAV
A (ADDRESS)
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGHQZ
tGLQV
tGLQX
Q (DATA OUT)
DATA VALID
tAVQV
MCM6706R
4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706R–6
MCM6706R–7
MCM6706R–8
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
tAVAV
6
—
7
—
8
—
ns
3
Address Setup Time
tAVWL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
6
—
7
—
8
—
ns
Write Pulse Width
tWLWH,
tWLEH
6
—
7
—
8
—
ns
Data Valid to End of Write
tDVWH
3
—
3.5
—
4
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
3.5
0
3.5
0
4
ns
4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns
4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
Parameter
Write Cycle Time
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
tDVWH
D (DATA IN)
tWHDX
DATA VALID
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MOTOROLA FAST SRAM
MCM6706R
5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6706R–6
MCM6706R–7
MCM6706R–8
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
tAVAV
6
—
7
—
8
—
ns
3
Address Setup Time
tAVEL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
6
—
7
—
8
—
ns
Chip Enable to End of Write
tELWH,
tELEH
5
—
6
—
7
—
ns
Data Valid to End of Write
tDVEH
3
—
3.5
—
4
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
Parameter
Write Cycle Time
4,5
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV
A (ADDRESS)
tAVEH
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
tEHAX
W (WRITE ENABLE)
tDVEH
D (DATA IN)
tEHDX
DATA VALID
HIGH–Z
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6706R
X
XX
XX
Motorola Memory Prefix
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Part Number
Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns)
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6706J6
MCM6706RJ6R2
MCM6706R
6
MCM6706RJ7
MCM6706RJ7R2
MCM6706RJ8
MCM6706RJ8R2
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32–LEAD
300 MIL SOJ
CASE 857–02
F 32 PL
0.17(0.007)
32
17
1
M
D 32 PL
0.17(0.007)
P
0.17(0.007) S B
16
-AL
G
DETAIL Z
A
S
S
NOTE 5
S
A
S
-B-X-
K
S
NOTE 4
NOTE 3
E C
0.10 (0.004)
-T-
SEATING
PLANE
R
0.25 (0.010)
S RADIUS
S
B
S
NOTE 5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DATUM PLANE -X- LOCATED AT TOP OF MOLD
PARTING LINE AND COINCIDENT WITH TOP OF
LEAD, WHERE LEAD EXITS BODY.
4. TO BE DETERMINED AT PLANE -X-.
5. TO BE DETERMINED AT PLANE -T-.
6. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
7. 857-01 IS OBSOLETE, NEW STANDARD 857-02.
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
MILLIMETERS
MIN
MAX
20.83 21.08
7.50
7.74
3.26
3.75
0.41
0.50
2.24
2.48
0.67
0.81
1.27 BSC
0.89
1.14
0.64 BSC
0.76
1.14
8.38
8.64
6.60
6.86
0.77
1.01
INCHES
MIN
MAX
0.820 0.830
0.295 0.305
0.128 0.148
0.016 0.020
0.088 0.098
0.026 0.032
0.050 BSC
0.035 0.045
0.025 BSC
0.030 0.045
0.330 0.340
0.260 0.270
0.030 0.040
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM6706R
7
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM6706R
8
◊
CODELINE TO BE PLACED HERE
*MCM6706R/D*
MCM6706R/D
MOTOROLA FAST
SRAM