MOTOROLA MPC940

SEMICONDUCTOR TECHNICAL DATA
" ! The MPC940 is a 1:18 low voltage clock distribution chip. The device
features the capability to select either a differential LVPECL or an LVTTL/
LVCMOS compatible input. The 18 outputs are LVCMOS or LVTTL
compatible and feature the drive strength to drive 50Ω series or parallel
terminated transmission lines. With output–to–output skews of 150ps, the
MPC940 is ideal as a clock distribution chip for the most demanding of
synchronous systems. For a similar product with a larger number of
outputs, please consult the MPC941 data sheet.
•
•
•
•
•
•
LOW VOLTAGE
1:18 CLOCK
DISTRIBUTION CHIP
LVPECL or LVCMOS/LVTTL Clock Input
150ps Maximum Targeted Output–to–Output Skew
Drives Up to 36 Independent Clock Lines
Maximum Output Frequency of 250MHz
32–Lead TQFP Packaging
3.3V VCC Supply Voltage
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
With a low output impedance (≈20Ω), in both the HIGH and LOW logic
states, the output buffers of the MPC940 are ideal for driving series
terminated transmission lines. More specifically, each of the 18 MPC940
outputs can drive two series terminated 50Ω transmission lines. With this
capability, the MPC940 has an effective fanout of 1:36 in applications
where each line drives a single load. With this level of fanout, the
MPC940 provides enough copies of low skew clocks for most high
performance synchronous systems.
The differential LVPECL inputs of the MPC940 allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC940 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
6/97
 Motorola, Inc. 1997
1
REV 0.2
MPC940
LOGIC DIAGRAM
PECL_CLK
PECL_CLK
0
LVCMOS_CLK
1
Q0
16
LVCMOS_CLK_Sel
Q1–Q16
Q17
Q6
Q7
Q8
VCCO
Q9
Q10
Q11
GND
Pinout: 32–Lead TQFP (Top View)
24
23
22
21
20
19
18
17
GNDO
25
16
VCCO
Q5
26
15
Q12
Q4
27
14
Q13
Q3
28
13
Q14
VCCO
29
12
GNDO
Q2
30
11
Q15
Q1
31
10
Q16
Q0
32
9
Q17
MOTOROLA
1
2
3
4
5
6
7
8
GNDO
GNDI
LVCMOS_CLK
LVCMOS_CLK_Sel
PECL_CLK
PECL_CLK
VCCI
VCCO
MPC940
2
FUNCTION TABLE
LVCMOS_CLK_Sel
0
1
Input
PECL_CLK
LVCMOS_CLK
TIMING SOLUTIONS
BR1333 — Rev 6
MPC940
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
125
°C
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
PECL_CLK
Other
2.135
2.0
2.42
3.60
V
VIL
Input LOW Voltage
PECL_CLK
Other
1.49
1.825
0.8
V
VPP
Peak–to–Peak Input Voltage
PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC–2.0
VCC–0.6
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
CIN
Input Capacitance
Cpd
Power Dissipation Capacitance
ICC
Maximum Quiescent Supply Current
2.5
V
IOH = –16mA, Note 1.
IOH = 16mA, Note 1.
0.5
V
±100
µA
4
pF
8
Condition
pF
Per Output
ICCL
70
mA
ICCH
140
1. The MPC940 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Fmax
Maximum Input Frequency
tpd
Propagation Delay
tsk(o)
Output–to–Output Skew
tsk(pr)
Part–to–Part Skew
tpwo
Output Pulse Width
Min
PECL_CLK to Q
TTL_CLK to Q
Typ
Max
Note 1.
1.7
2.0
ns
Note 1.
ps
Note 1.
ps
Notes 2., 3.
p%
Note 1.,
Measured at VCC/2
800
800
45
Condition
MHz
150
PECL_CLK to Q
TTL_CLK to Q
Unit
250
55
tr, tf
Output Rise/Fall Time
0.20
1.0
ns
0.8V to 2.0V
1. Driving 50Ω transmission lines
2. Part–to–part skew at a given temperature and voltage
3. Final specification limits will be determined from matrix lot material. 800ps is the “best estimate” based on initial material and experience with
previous products.
TIMING SOLUTIONS
BR1333 — Rev 6
3
MOTOROLA
MPC940
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
D
SECTION AE–AE
W
K
X
DETAIL AD
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
MOTOROLA
M
N
0.20 (0.008)
SEATING
PLANE
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
TIMING SOLUTIONS
BR1333 — Rev 6
MPC940
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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TIMING SOLUTIONS
BR1333 — Rev 6
◊
5
MPC940/D
MOTOROLA