MOTOROLA MTSF3N02HD

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SEMICONDUCTOR TECHNICAL DATA
 Medium Power Surface Mount Products
Motorola Preferred Device
Micro8 devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process to
achieve lowest possible on–resistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the drain–to–source diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dc–dc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
• Miniature Micro8 Surface Mount Package — Saves Board Space
• Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for Micro8 Package Provided
DEVICE MARKING
AC
SINGLE TMOS
POWER MOSFET
4.0 AMPERES
20 VOLTS
RDS(on) = 0.040 OHM

D
CASE 846A–02, Style 1
Micro8
G
S
Source
1
8
Drain
Source
2
7
Drain
Source
3
6
Drain
Gate
4
5
Drain
Top View
ORDERING INFORMATION
Device
MTSF3N02HDR2
Reel Size
Tape Width
Quantity
13″
12 mm embossed tape
4000 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Micro8 is a registered trademark of International
Rectifier. Thermal Clad is a trademark of the Bergquist Company.
REV 4
TMOS
Motorola
Motorola, Inc.
1997 Power MOSFET Transistor Device Data
1
MTSF3N02HD
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
1 inch SQ.
FR–4 or G–10 PCB
Figure 1 below
Steady State
Minimum
FR–4 or G–10 PCB
Figure 2 below
Steady State
Thermal Resistance — Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current — Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (1)
Thermal Resistance — Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current — Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (1)
Operating and Storage Temperature Range
Symbol
Max
Unit
VDSS
VDGR
VGS
20
V
20
V
RTHJA
PD
ID
ID
IDM
RTHJA
PD
ID
ID
IDM
TJ, Tstg
± 8.0
V
70
1.79
14.29
6.1
4.9
49
°C/W
Watts
mW/°C
A
A
A
160
0.78
6.25
4.0
3.2
32
°C/W
Watts
mW/°C
A
A
A
– 55 to 150
°C
(1) Repetitive rating; pulse width limited by maximum junction temperature.
Figure 1. 1.0 Inch Square FR–4 or G–10 PCB
2
Figure 2. Minimum FR–4 or G–10 PCB
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
20
—
—
16
—
—
—
—
—
—
1.0
25
—
—
100
0.7
—
0.98
2.65
1.1
—
—
—
30
40
40
50
gFS
4.0
7.5
—
Mhos
Ciss
—
475
—
pF
Coss
—
255
—
Crss
—
110
—
td(on)
—
9.5
—
tr
—
45
—
td(off)
—
50
—
tf
—
62
—
td(on)
—
19
—
tr
—
130
—
td(off)
—
38
—
tf
—
47
—
QT
—
12
17
Q1
—
1.0
—
Q2
—
5.0
—
Q3
—
3.5
—
—
—
0.83
0.68
1.0
—
trr
—
46
—
ta
—
23
—
tb
—
23
—
QRR
—
0.05
—
OFF CHARACTERISTICS
(Cpk ≥ 2.0)
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
(1) (3)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0)
Static Drain–to–Source On–Resistance
(VGS = 4.5 Vdc, ID = 3.8 Adc)
(VGS = 2.7 Vdc, ID = 1.9 Adc)
(Cpk ≥ 2.0)
Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc)
(3)
(3)
(1)
VGS(th)
Vdc
RDS(on)
mV/°C
mΩ
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 15 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
((VDS = 10 Vdc,
Vd , ID = 3.8
3 8 Adc,
Ad ,
VGS = 4.5 Vdc, RG = 6 Ω) (1)
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
((VDD = 10 Vdc,
Vd , ID = 1.9
1 9 Adc,
Ad ,
VGS = 2.7 Vdc, RG = 6 Ω) (1)
Fall Time
Gate Charge
((VDS = 16 Vdc,
Vd , ID = 3.8
3 8 Adc,
Ad ,
VGS = 4.5 Vdc)
ns
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 3.8 Adc, VGS = 0 Vdc) (1)
(IS = 3.8 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 3
3.8
8 Adc
Adc, VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/µs) (1)
Reverse Recovery Storage Charge
VSD
Vdc
ns
µC
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk =
3 x SIGMA
Motorola TMOS Power MOSFET Transistor Device Data
3
MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
8
8
5
I D , DRAIN CURRENT (AMPS)
6
1.7 V
4
3
1.5 V
2
6
5
4
3
25°C
1
0
0
0.4
0.8
1.6
1.2
2
TJ = –55°C
2
1
0
VDS ≥ 10 V
7
1.9 V
100°C
1
1.8
Figure 4. Transfer Characteristics
VGS = 3.8 V
TJ = 25°C
0.05
0.04
0.03
0.02
0.01
0
2
4
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
8
2
0.06
TJ = 25°C
0.05
VGS = 2.7 V
0.04
4.5 V
0.03
0.02
0.01
0
1
2
3
5
4
6
7
8
ID, DRAIN CURRENT (AMPS)
Figure 6. On–Resistance versus Drain Current
and Gate Voltage
2.0
1000
VGS = 4.5 V
ID = 1.9 A
VGS = 0 V
1.5
I DSS , LEAKAGE (nA)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
1.6
Figure 3. On–Region Characteristics
Figure 5. On–Resistance versus
Gate–to–Source Voltage
4
1.4
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
0.06
1.0
0.5
0
– 50
1.2
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
7
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
TJ = 25°C
VGS = 10 V
4.5 V
2.9 V
2.5 V
2.3 V
2.1 V
100
100°C
10
1
0.1
– 25
0
25
50
75
100
125
150
TJ = 125°C
25°C
0
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. On–Resistance Variation
with Temperature
Figure 8. Drain–to–Source Leakage Current
versus Voltage
20
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2500
TJ = 25°C
VGS = 0 V
Ciss
C, CAPACITANCE (pF)
2000
Crss
1500
1000
Ciss
Coss
500
0
8
4
Crss
4
0
VGS
8
12
16
20
VDS
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 9. Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
5
18
QT
5
VGS
VDS
4
3
Q1
15
12
9
Q2
6
2
1
ID = 3.8 A
TJ = 25°C
Q3
0
0
3
6
9
Qg, TOTAL GATE CHARGE (nC)
3
0
15
12
1000
VDD = 10 V
ID = 3.8 A
VGS = 4.5 V
TJ = 25°C
100
t, TIME (ns)
6
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTSF3N02HD
tr
tf
td(off)
td(on)
10
1
1
10
RG, GATE RESISTANCE (OHMS)
Figure 10. Gate–To–Source and
Drain–To–Source Voltage versus Total Charge
100
Figure 11. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 14. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
4
I S , SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
3
2
1
0
0.4
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 12. Diode Forward Voltage versus Current
6
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
di/dt = 300 A/µs
Standard Cell Density
trr
I S , SOURCE CURRENT
High Cell Density
trr
tb
ta
t, TIME
Figure 13. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased.
Curves are based upon maximum peak junction temperature
and a case temperature (TC) of 25°C. Peak repetitive pulsed
power limits are determined by using the thermal response data
in conjunction with the procedures discussed in AN569, “Tran-
I D , DRAIN CURRENT (AMPS)
100
10
VGS = 8 V
SINGLE PULSE
TC = 25°C
sient Thermal Resistance – General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded, and that the
transition time (t r, t f ) does not exceed 10 µs. In addition
the total power averaged over a complete switching cycle
must not exceed (T J(MAX) – T C )/(RθJC ).
100 µs
1 ms
10 ms
1
dc
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 14. Maximum Rated Forward Biased
Safe Operating Area
Motorola TMOS Power MOSFET Transistor Device Data
7
MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE ( °C/W)
1000
100
10
D = 0.5
0.2
0.1
0.05
P(pk)
0.02
0.01
1.0
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.1
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
t, TIME (s)
1.0E+00
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+01
1.0E+02
1.0E+03
Figure 15. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 16. Diode Reverse Recovery Waveform
8
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.
0.041
1.04
0.208
5.28
0.015
0.38
0.126
3.20
0.0256
0.65
inches
mm
Micro8 POWER DISSIPATION
The power dissipation of the Micro8 is a function of the input
pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from the
device junction to ambient; and the operating temperature, TA.
Using the values provided on the data sheet for the Micro8
package, PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this case
is 0.78 Watts.
PD = 150°C – 25°C = 0.78 Watts
160°C/W
The 160°C/W for the Micro8 package assumes the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 0.78 Watts using the footprint
shown. Another alternative would be to use a ceramic
substrate or an aluminum core board such as Thermal Clad.
Using board material such as Thermal Clad, the power
dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
Motorola TMOS Power MOSFET Transistor Device Data
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
9
MTSF3N02HD
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
14 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems, but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 –189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 6
VENT
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
“SPIKE”
“SOAK”
170°C
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
160°C
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 17. Typical Solder Heating Profile
10
Motorola TMOS Power MOSFET Transistor Device Data
MTSF3N02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
1.60 (.063)
1.50 (.059)
2.05 (.080)
1.95 (.077)
PIN
NUMBER 1
4.10 (.161)
3.90 (.154)
B
B
1.85 (.072)
1.65 (.065)
A
0.35 (.013)
0.25 (.010)
5.55 (.218)
5.45 (.215)
12.30
11.70
(.484)
(.461)
3.50 (.137)
3.30 (.130)
1.60 (.063)
1.50 (.059)
TYP.
A
FEED DIRECTION
8.10 (.318)
7.90 (.312)
1.50 (.059)
1.30 (.052)
SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
1. CONFORMS TO EIA–481–1.
2. CONTROLLING DIMENSION: MILLIMETER.
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0
(13.20)
MAX.
NOTES:
1. CONFORMS TO EIA–481–1.
2. CONTROLLING DIMENSION: MILLIMETER.
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.
Motorola TMOS Power MOSFET Transistor Device Data
50.0
(1.97)
MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
11
MTSF3N02HD
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION D DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
–A–
–B–
K
PIN 1 ID
G
D 8 PL
0.13 (0.005)
–T–
M
T B
S
A
S
SEATING
PLANE
0.038 (0.0015)
C
H
J
L
DIM
A
B
C
D
G
H
J
K
L
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
–––
1.10
0.25
0.40
0.65 BSC
0.05
0.15
0.13
0.23
4.75
5.05
0.40
0.70
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
–––
0.043
0.010
0.016
0.026 BSC
0.002
0.006
0.005
0.009
0.187
0.199
0.016
0.028
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
CASE 846A–02
ISSUE B
MICRO8
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Mfax is a trademark of Motorola, Inc.
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12
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MTSF3N02HD/D
Motorola TMOS Power MOSFET Transistor
Device Data