SN54/74LS165 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) J SUFFIX CERAMIC CASE 620-09 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 PIN NAMES LOADING (Note a) HIGH CP1, CP2 DS PL P0 – P7 Q7 Q7 Clock (LOW-to-HIGH Going Edge) Inputs Serial Data Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Serial Output from Last State (Note b) Complementary Output (Note b) LOW 0.5 U.L. 0.5 U.L. 1.5 U.L. 0.25 U.L. 0.25 U.L. 0.75 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 16 1 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. CONTENTS PL L H H H H Ceramic Plastic SOIC LOGIC SYMBOL TRUTH TABLE CP D SUFFIX SOIC CASE 751B-03 RESPONSE 1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 X L H X P0 DS Q0 DS Q0 P1 Q0 Q1 Q0 Q1 P2 Q1 Q2 Q1 Q2 P3 Q2 Q3 Q2 Q3 P4 Q3 Q4 Q3 Q4 P5 Q4 Q5 Q4 Q5 P6 Q5 Q6 Q5 Q6 P7 Q6 Q7 Q6 Q7 L H Parallel Entry Right Shift No Change Right Shift No Change H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 5-290 SN54/74LS165 LOGIC DIAGRAM FUNCTIONAL DESCRIPTION The SN54/74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup and hold times are observed. For clock operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-291 SN54/74LS165 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Parameter Typ 54 0.7 74 0.8 – 0.65 IOS Short Circuit Current (Note 1) ICC Power Supply Current – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 60 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 1.2 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 36 mA VCC = MAX Other Inputs PL Input Input LOW Current Other Inputs PL Input Unit 2.0 Input HIGH Current Other Inputs PL Input IIL Max 0.1 0.3 – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 35 Max Unit fMAX Maximum Input Clock Frequency tPLH tPHL Propagation Delay PL to Output 22 22 35 35 ns tPLH tPHL Propagation Delay Clock to Output 27 28 40 40 ns tPLH tPHL Propagation Delay P7 to Q7 14 21 25 30 ns tPLH tPHL Propagation Delay P7 to Q7 21 16 30 25 ns MHz FAST AND LS TTL DATA 5-292 Test Conditions VCC = 5.0 V CL = 15 pF SN54/74LS165 AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit tW CP Clock Pulse Width 25 ns tW PL Pulse Width 15 ns ts Parallel Data Setup Time 10 ns ts Serial Data Setup Time 20 ns ts CP1 to CP2 Setup Time1 30 ns th Hold Time 0 ns trec Recovery Time, PL to CP 45 ns Test Conditions VCC = 5.0 V 1 The role of CP , and CP in an application may be interchanged. 1 2 DEFINITION OF TERMS: SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs. AC WAVEFORMS Figure 1 Figure 2 Figure 3 Figure 4 FAST AND LS TTL DATA 5-293 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-294 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! " " -B1 & 9 * * ! ! ! ! * * ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-295