Freescale Semiconductor, Inc. HYBRID MCU/DSP 56857 120 MIPS Hybrid Processor Freescale Semiconductor, Inc... TARGET APPLICATIONS • Multi-processor Telephony Systems • Stand-alone MP3 player • DTAD • Feature phone • Voice recognition and command • Embedded modem/data pump • LCD and keypad support • General purpose devices • Automotive hands-free BENEFITS • Supports multiple processor connections • Flexible 6-Channel Direct Memory Access (DMA) allows both internal and external memory transfers with almost no CPU interruption • 16-bit quad timer module (with four external pins) that allows capture/compare functionality, and can be cascaded • Serial peripheral interface with master and slave mode supporting connection to other processors or serial memory devices • Quad timer module can also be used for simple digital-to-analog conversion functionality • Two enhanced synchronous serial interfaces with three transmitters per module provide support for 5.1 channel surround sound for audio applications • Easy to program with flexible application development tools • Enhanced synchronous serial interface with enhanced network and audio modes • Time of Day for applications requiring clock display The 56857 offers a rich feature set and on-chip memory in a 100-pin LQFP. It includes 80 KB of on-chip program SRAM and 48 KB of on-chip data SRAM. With two enhanced serial synchronous serial interfaces (ESSIs), this device can provide outputs for 5.1-channel surround sound. The 56857 can be designed into multi-processor systems to provide internet audio and speech processing functionalities. 56857 16-BIT DIGITAL SIGNAL PROCESSORS • 120 MIPS at 120MHz • 8-bit parallel Host Interface • 80 KB Program SRAM • General purpose 16-bit Quad Timer • 48 KB Data SRAM • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • 2 KB Boot ROM • Six independent channels of DMA • Two Enhanced Synchronous Serial Interfaces (ESSI) • Two Serial Communication Interfaces (SCI) • Serial Peripheral Interface (SPI) COP/Watchdog • Computer Operating Properly (COP)/Watchdog Timer • Time of Day (TOD) • 100-pin LQFP package • Up to 47 GPIO • Four dedicated GPIO Program Memory ENERGY INFORMATION 80 KB SRAM SPI 6-channel DMA Prog Chip Selects 2 KB Boot ROM (2) SCI (2) ESSI Up to 47 GPIO 16-Bit Quad Timer • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs 56800E Core 120 MIPS Time of Day Data Memory PLL 48 KB SRAM JTAG/EOnCE 8-Bit Host For More Information On This Product, Go to: www.freescale.com • Wait and Stop modes available Freescale Semiconductor, Inc. 56800E CORE FEATURES HYBRID MCU/DSP The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers, enabling rapid development of optimized control applications. Features of the 56800E core include: 56857 PRODUCT DOCUMENTATION DSP56800E Reference Manual Freescale Semiconductor, Inc... DSP5685x User’s Manual DSP56857 Technical Data Sheet Detailed description of the 56800E architecture, 16-bit DSP core processor and the instruction set • Efficient 16-bit hybrid controller engine with dual Harvard architecture • Four internal data buses and one external data bus Order Number: DSP56800ERM/D • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Instruction set supports both DSP and controller functions Detailed description of memory, peripherals, and interfaces of the 56853, 56854, 56855, 56857, and 56858 • Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) • Four hardware interrupt levels Order Number: DSP5685xUM/D • Four (4) 36-bit accumulators, including extension bits • Controller-style addressing modes and instructions for compact code • 16-bit bidirectional shifter • Efficient C compiler and local variable support Electrical and timing specifications, pin descriptions, and package descriptions • Hardware DO and REP loops • Software subroutine and interrupt stack with depth limited only by memory Summary description and block diagram of the core, memory, peripherals and interfaces • Three internal address buses and one external address bus • JTAG/Enhanced OnCE debug programming interface Order Number: DSP56857PB/D 56857 MEMORY FEATURES Order Number: DSP56857/D DSP56857 Product Brief • Parallel instruction set with unique addressing modes • Five software interrupt levels • On-chip Memory – 80 KB Program RAM – 48 KB Data RAM AWARD-WINNING DEVELOPMENT ENVIRONMENT • Harvard architecture permits up to three simultaneous accesses to program and data memory – 2 KB Boot ROM • Processor Expert™ (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. • The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. – Chip Select Logic used as GPIO 56857 PERIPHERAL CIRCUIT FEATURES • General Purpose 16-bit Quad Timer* • Six independent channels of DMA • Two Serial Communication Interfaces (SCI)* • 8-bit parallel Host Interface* • Serial Peripheral Interface (SPI) Port* • Four dedicated GPIO • Two Enhanced Synchronous Serial Interface (ESSI) modules* • Up to 47 GPIO • Computer Operating Properly (COP)/Watchdog Timer * Each peripheral I/O can be used alternately as a General Purpose I/O • Time of Day (TOD) • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging ORDERING INFORMATION PART SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER DSP56857 DSP56857 1.8V, 3.3V 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) Low-Profile Quad Flat Pack (LQFP) 100 100 120 120 DSP56857BU120 SPAK56857BU120 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56857PB/D REV 3 For More Information On This Product, Go to: www.freescale.com