Freescale Semiconductor, Inc. HYBRID FLASH SOLUTION 56F805 16-bit Hybrid Controller Freescale Semiconductor, Inc... TARGET APPLICATIONS • • • • • • • • • • • Regenerative drives ID tag readers Winders/pullers Glass breakage detection Critical reliability drives Cable test equipment HVAC Remote monitoring Automotive control General purpose devices Switched-mode power supplies BENEFITS • On-board voltage regulator and power management is designed to reduce overall system cost by allowing for a single supply voltage • Flash memory is engineered to provide reliable, non-volatile memory storage, eliminating the need for external storage devices • Supports multiple processor connections • Patented distortion correction in PWM for reducing design risk and better performance control • PWM and ADC modules are tightly coupled to reduce processing overhead • Easy to program with flexible application development tools • Low voltage interrupts protect the system during brownout or power failure • Simple updating of Flash memory through SPI, SCI or OnCE™, using on-chip boot loader • Simple interface with other asynchronous serial communication devices and off-chip EE memory • Program can boot directly from Flash The 56F805 is a member of the 56800 core-based family of Hybrid Controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F805 is well-suited for many applications. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. 56F805 16-BIT HYBRID CONTROLLER • Up to 40 MIPS at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Up to 64K each of external program and data memory • Two 6-channel PWM modules • Hardware DO and REP loops • Two 4-channel, 12-bit ADCs • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • Two Quadrature Decoders • 38K On-chip Flash - 32K Program Flash - 4K Data Flash - 2K Boot Flash • 512 Program RAM • 2K Data RAM • CAN 2.0 A/B module • Two Serial Communication Interfaces (SCIs) • Serial Peripheral Interface (SPI) • Four general purpose Quad Timers • JTAG/OnCE port for debugging • 14 dedicated and 18 shared GPIO lines • 144-pin LQFP Package ENERGY INFORMATION COP/Watchdog Program Memory Ext Memory I/F 512 RAM 32K Flash • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Uses a single 3.3V power supply • Wait and Stop modes available SPI 2K Boot Flash (2) SCI 56800 Core CAN 2.0 A/B Up to 32 GPIO (4) 16-Bit Quad Timers 40 MIPS Dual 4-Channel ADC, 12-Bit Power Mgmt Data Memory (2) 6-Channel PWM PLL 2K RAM JTAG/OnCE (2) 4-Channel Quad Decoder 4K Flash For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 56800 CORE FEATURES HYBRID FLASH SOLUTION • Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture 56F805 PRODUCT DOCUMENTATION • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency DSP56800 Family Manual • Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Detailed description of the 56800 family architecture, and 16-bit DSP core processor and the instruction set Order Number: DSP56800FM/D DSP56F80x User’s Manual Detailed description of memory, peripherals, and interfaces of the 56F801, 56F802, 56F803, 56F805, and 56F807 Freescale Semiconductor, Inc... Order Number: DSP56F801-07UM/D DSP56F805 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions Order Number: DSP56F805/D DSP56F805 Product Brief Summary description and block diagram of the core, memory, peripherals and interfaces Order Number: DSP56F805PB/D • Two 36-bit accumulators, including extension bits • Four internal data buses and one external data bus • Instruction set supports both DSP and controller functions • Controller-style addressing modes and instructions for compact code • Efficient C compiler and local variable support • 16-bit bidirectional barrel shifter • Software subroutine and interrupt stack with depth limited only by memory • Parallel instruction set with unique addressing modes • JTAG/OnCE debug programming interface • Hardware DO and REP loops • Three internal address buses and one external address bus 56F805 MEMORY FEATURES • Harvard architecture permits as many as three simultaneous accesses to program and data memory • On-chip memory including a low-cost, high-volume Flash solution • Off-chip memory expansion capabilities – As much as 64K data memory – As much as 64K program memory - 38K On-chip Flash - 32K Program Flash - 4K Data Flash AWARD-WINNING DEVELOPMENT ENVIRONMENT - 2K Boot Flash - 512 Program RAM • Processor Expert™ (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. • The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. - 2K Data RAM 56F805 PERIPHERAL CIRCUIT FEATURES • Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault-tolerant design with dead-time insertion; supports both center- and edge- aligned modes • Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and PWM modules can be synchronized • Two Quadrature Decoders • CAN 2.0 A/B module • Serial Peripheral Interface (SPI) • 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins • Computer Operating Properly (COP)/ Watchdog timer • Two dedicated external interrupt pins • External reset input pin for hardware reset • External reset output pin for system reset • Four general purpose Quad Timers • JTAG/OnCE™ module for unobtrusive, processor speed-independent debugging • Two Serial Communication Interfaces (SCI) • Software-programmable, Phase Lock Loop-based frequency synthesizer ORDERING INFORMATION PART SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER DSP56F805 DSP56F805 3.0–3.6V 3.0–3.6V Low-profile Quad Flat Pack (LQFP) Low-profile Quad Flat Pack (LQFP) 144 144 80 80 DSP56F805FV80 SPAK56F805FV80 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56F805PB/D For More Information On This Product, REV 6 Go to: www.freescale.com