Freescale Semiconductor, Inc. HYBRID FLASH SOLUTION 56F807 16-bit Hybrid Controller Freescale Semiconductor, Inc... TARGET APPLICATIONS • • • • • • • • • • Conveyors UPS Servo drives Fuel management systems Lifts/elevators/cranes Underwater acoustics Industrial frequency inverters Noise cancellation General purpose devices Switched-mode power supplies BENEFITS • On-board voltage regulator and power management is designed to reduce overall system cost by allowing for a single supply voltage • Supports multiple processor connections • Flash memory is engineered to provide reliable, non-volatile memory storage, eliminating the need for external storage devices • PWM and ADC modules are tightly coupled to reduce processing overhead • Easy to program with flexible application development tools • Simple updating of Flash memory through SPI, SCI or OnCE™, using on-chip boot loader • Patented distortion correction in PWM for reducing design risk and better performance control • Low voltage interrupts protect the system during brownout or power failure • Simple interface with other asynchronous serial communication devices and off-chip EE memory • Program can boot directly from Flash The 56F807 is a member of the 56800 core-based family of Hybrid Controllers. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F807 is well-suited for many applications. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for compilers to enable rapid development of optimized control applications. 56F807 16-BIT HYBRID CONTROLLER • Up to 40 MIPS at 80MHz core frequency • Two 6 channel PWM modules • DSP and MCU functionality in a unified, C-efficient architecture • Four 4 channel, 12-bit ADCs • Hardware DO and REP loops • CAN 2.0 A/B module • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • Two Serial Communication Interfaces (SCIs) • 70K On-chip Flash - 60K Program Flash - 8K Data Flash - 2K Boot Flash • Two Quadrature Decoders • Serial Peripheral Interface (SPI) • Four general purpose Quad Timers • JTAG/OnCE port for debugging • 14 dedicated and 18 shared GPIO lines • 160-pin LQFP or 160 MAPBGA Packages • 2K Program RAM • 4K Data RAM COP/Watchdog ENERGY INFORMATION Program Memory Ext Memory I/F 2K RAM 60K Flash • Fabricated in high-density CMOS with 5Vtolerant, TTL-compatible digital inputs • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Uses a single 3.3V power supply • Wait and Stop modes available SPI 2K Boot Flash (2) SCI 56800 Core CAN 2.0 A/B Up to 32 GPIO (4) 16-Bit Quad Timers 40 MIPS Quad 4-Channel ADC, 12-Bit Power Mgmt Data Memory (2) 4-Channel Quad Decoder (2) 6-Channel PWM PLL 4K RAM 8K Flash JTAG/OnCE For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 56800 CORE FEATURES HYBRID FLASH SOLUTION • Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture 56F807 • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency PRODUCT DOCUMENTATION DSP56800 Family Manual Freescale Semiconductor, Inc... DSP56F80x User’s Manual DSP56F807 Technical Data Sheet DSP56F807 Product Brief Detailed description of the 56800 family architecture, and 16-bit DSP core processor and the instruction set Order Number: DSP56800FM/D Detailed description of memory, peripherals, and interfaces of the 56F801, 56F802, 56F803, 56F805, and 56F807 Order Number: DSP56F801-7UM/D Electrical and timing specifications, pin descriptions, and package descriptions Order Number: DSP56F807/D Summary description and block diagram of the core, memory, peripherals and interfaces Order Number: DSP56F807PB/D • Single-cycle 16 x 16-bit parallel MultiplierAccumulator (MAC) • Two 36-bit accumulators including extension bits • Three internal address buses and one external address bus • Four internal data buses and one external data bus • Instruction set supports both DSP and controller functions • Controller-style addressing modes and instructions for compact code • 16-bit bidirectional barrel shifter • Efficient C compiler and local variable support • Parallel instruction set with unique addressing modes • Software subroutine and interrupt stack with depth limited only by memory • Hardware DO and REP loops • JTAG/OnCE debug programming interface 56F807 MEMORY FEATURES • Harvard architecture permits as many as three simultaneous accesses to program and data memory • On-chip memory including a low-cost, high-volume Flash solution • Off-chip memory expansion capabilities – As much as 64K data memory – As much as 64K program memory - 70K On-chip Flash - 60K Program Flash - 8K Data Flash - 2K Boot Flash - 2K Program RAM AWARD-WINNING DEVELOPMENT ENVIRONMENT - 4K Data RAM • Processor Expert™ (PE) technology provides a rapid application design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. • The CodeWarrior™ Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling and debugging. A comprehensive set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, the CodeWarrior tool suite and EVMs create a comprehensive, scalable tools solution for easy, fast and efficient development. 56F807 PERIPHERAL CIRCUIT FEATURES • Two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault-tolerant design with dead-time insertion; supports both center- and edge-aligned modes • Four 12-bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and PWM modules can be synchronized • Two Quadrature Decoders • Four dedicated General Purpose Quad Timers • Two Serial Communication Interfaces (SCI) • Serial Peripheral Interface (SPI) • Computer Operating Properly (COP)/ Watchdog timer • Two dedicated external interrupt pins • 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins • External reset input pin for hardware reset • External reset output pin for system reset • JTAG/OnCE™ for unobtrusive, processor speed-independent debugging • Software-programmable, Phase Lock Loop-based frequency synthesizer • CAN 2.0 A/B module ORDERING INFORMATION PART DSP56F807 DSP56F807 DSP56F807 DSP56F807 SUPPLY VOLTAGE PACKAGE TYPE PIN COUNT FREQUENCY (MHz) ORDER NUMBER 3.0–3.6V 3.0–3.6V 3.0–3.6V 3.0–3.6V Low profile Quad Flat Pack (LQFP) MAP Ball Grid Array (MAPBGA) Low profile Quad Flat Pack (LQFP) MAP Ball Grid Array (MAPBGA) 160 160 160 160 80 80 80 80 DSP56F807PY80 DSP56F807VF80 SPAK56F807PY80 SPAK56F807VF80 Motorola and the stylized M Logo are registered in the U.S. Patent and Trademark Office. This product incorporates SuperFlash® technology licensed from SST. All other product or service names are the property of their respective owners. © Motorola, Inc. 2003 DSP56F807PB/D For More Information REV 6 On This Product, Go to: www.freescale.com