Order this document by BAS40LT1/D SEMICONDUCTOR TECHNICAL DATA These Schottky barrier diodes are designed for high speed switching applications, circuit protection, and voltage clamping. Extremely low forward voltage reduces conduction loss. Miniature surface mount package is excellent for hand held and portable applications where space is limited. 3 CATHODE 1 ANODE Motorola Preferred Device 40 VOLTS SCHOTTKY BARRIER DIODES 3 1 2 CASE 318 – 08, STYLE 8 SOT– 23 (TO – 236AB) MAXIMUM RATINGS (TJ = 150°C unless otherwise noted) Rating Symbol Value Unit Reverse Voltage VR 40 Volts Forward Power Dissipation @ TA = 25°C Derate above 25°C PF 225 1.8 mW mW/°C – 55 to +150 °C Operating Junction and Storage Temperature Range TJ, Tstg DEVICE MARKING BAS40LT1 = B1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit Reverse Breakdown Voltage (IR = 10 µA) V(BR)R 40 — Volts Total Capacitance (VR = 1.0 V, f = 1.0 MHz) CT — 5.0 pF Reverse Leakage (VR = 25 V) IR — 1.0 µAdc Forward Voltage (IF = 0.1 mAdc) VF — 380 mVdc Forward Voltage (IF = 30 mAdc) VF — 500 mVdc Forward Voltage (IF = 100 mAdc) VF — 1.0 Vdc Preferred devices are Motorola recommended choices for future use and best overall value. Thermal Clad is a registered trademark of the Bergquist Company. REV 1 Motorola Small–Signal Transistors, FETs and Diodes Device Data Motorola, Inc. 1997 1 BAS40LT1 100 IR , REVERSE CURRENT (µA) IF, FORWARD CURRENT (mA) 100 10 150°C 1.0 1 25°C 85°C 25°C – 40°C 0.1 125°C 10 85°C 1.0 0.1 25°C 0.01 0.1 0 TA = 150°C 0.2 0.3 – 55°C 0.4 0.001 0.5 0.6 0.7 0 0.8 5.0 VF, FORWARD VOLTAGE (VOLTS) Figure 1. Typical Forward Voltage 10 15 VR, REVERSE VOLTAGE (VOLTS) 20 25 Figure 2. Reverse Current versus Reverse Voltage 3.5 C T, CAPACITANCE (pF) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5.0 10 15 20 25 30 35 40 VR, REVERSE VOLTAGE (VOLTS) Figure 3. Typical Capacitance 2 Motorola Small–Signal Transistors, FETs and Diodes Device Data BAS40LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. Motorola Small–Signal Transistors, FETs and Diodes Device Data 3 BAS40LT1 PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 B S 1 V 2 DIM A B C D G H J K L S V G C H D INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 J K STYLE 8: PIN 1. ANODE 2. NO CONNECTION 3. CATHODE CASE 318–08 ISSUE AE SOT–23 (TO–236AB) Motorola reserves the right to make changes without further notice to any products herein. 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